JPS5685167A - Data process system - Google Patents

Data process system

Info

Publication number
JPS5685167A
JPS5685167A JP16186279A JP16186279A JPS5685167A JP S5685167 A JPS5685167 A JP S5685167A JP 16186279 A JP16186279 A JP 16186279A JP 16186279 A JP16186279 A JP 16186279A JP S5685167 A JPS5685167 A JP S5685167A
Authority
JP
Japan
Prior art keywords
machine check
flag
arithmetic
conflict
reset
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16186279A
Other languages
Japanese (ja)
Inventor
Mikio Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16186279A priority Critical patent/JPS5685167A/en
Publication of JPS5685167A publication Critical patent/JPS5685167A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To realize a rewriting action, by applying a machine check interruption when a logical conflict is detected and at the same time resetting a function block having a conflict by detecting the logical conflict the working conditions of one function block and the other one.
CONSTITUTION: Both the flags 5 and 6 are reset in case, e.g., the arithmetic part 3 becomes idle without generating any arithmetic end signal by some reason after the instruction control part 2 produced an arithmetic command to the part 3. In such case, the output of the AND gate 7 becomes "1" with the machine check flag 8 being set. Then the machine check interruption circuit (not shown in the diagram) is started to inform the program that the machine check state is caused. Furthermore, both the part 3 and the flag 5 are reset by the output of the flag 8. In such way, the hang state is cancelled to realize a rewriting action.
COPYRIGHT: (C)1981,JPO&Japio
JP16186279A 1979-12-13 1979-12-13 Data process system Pending JPS5685167A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16186279A JPS5685167A (en) 1979-12-13 1979-12-13 Data process system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16186279A JPS5685167A (en) 1979-12-13 1979-12-13 Data process system

Publications (1)

Publication Number Publication Date
JPS5685167A true JPS5685167A (en) 1981-07-11

Family

ID=15743366

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16186279A Pending JPS5685167A (en) 1979-12-13 1979-12-13 Data process system

Country Status (1)

Country Link
JP (1) JPS5685167A (en)

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