JPS5685167A - Data process system - Google Patents
Data process systemInfo
- Publication number
- JPS5685167A JPS5685167A JP16186279A JP16186279A JPS5685167A JP S5685167 A JPS5685167 A JP S5685167A JP 16186279 A JP16186279 A JP 16186279A JP 16186279 A JP16186279 A JP 16186279A JP S5685167 A JPS5685167 A JP S5685167A
- Authority
- JP
- Japan
- Prior art keywords
- machine check
- flag
- arithmetic
- conflict
- reset
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Debugging And Monitoring (AREA)
Abstract
PURPOSE: To realize a rewriting action, by applying a machine check interruption when a logical conflict is detected and at the same time resetting a function block having a conflict by detecting the logical conflict the working conditions of one function block and the other one.
CONSTITUTION: Both the flags 5 and 6 are reset in case, e.g., the arithmetic part 3 becomes idle without generating any arithmetic end signal by some reason after the instruction control part 2 produced an arithmetic command to the part 3. In such case, the output of the AND gate 7 becomes "1" with the machine check flag 8 being set. Then the machine check interruption circuit (not shown in the diagram) is started to inform the program that the machine check state is caused. Furthermore, both the part 3 and the flag 5 are reset by the output of the flag 8. In such way, the hang state is cancelled to realize a rewriting action.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16186279A JPS5685167A (en) | 1979-12-13 | 1979-12-13 | Data process system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP16186279A JPS5685167A (en) | 1979-12-13 | 1979-12-13 | Data process system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5685167A true JPS5685167A (en) | 1981-07-11 |
Family
ID=15743366
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP16186279A Pending JPS5685167A (en) | 1979-12-13 | 1979-12-13 | Data process system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5685167A (en) |
-
1979
- 1979-12-13 JP JP16186279A patent/JPS5685167A/en active Pending
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JPS5443644A (en) | Processing system for deadlock automatic release at exclusive control time | |
JPS54107645A (en) | Information processor | |
JPS5685167A (en) | Data process system | |
JPS5336439A (en) | Information processor | |
JPS55110328A (en) | Interrupt processing system | |
JPS5259537A (en) | Data processor | |
JPS5591040A (en) | Runaway monitor system for microprocessor | |
JPS52140243A (en) | Information processing unit containing use | |
JPS537152A (en) | Address stop circuit | |
JPS55119750A (en) | Processor providing test address function | |
JPS538525A (en) | Address designation system | |
JPS5697169A (en) | Multidata processing system | |
JPS55140920A (en) | Initial program load control system | |
JPS5561858A (en) | Central operation control unit | |
JPS5363829A (en) | Generation control system of interrupt signal and interrupt circuit its execution | |
JPS553011A (en) | Error processing system for sequence control unit | |
JPS5720828A (en) | Computer system | |
JPS5310929A (en) | Starting system of computer | |
JPS52130258A (en) | Test circuit for computers | |
JPS5453842A (en) | Program run control circuit | |
JPS52106245A (en) | Control system for digital logical circuit | |
JPS5552161A (en) | Information processing system | |
JPS5636754A (en) | Debugging system | |
JPS5299032A (en) | Console control method | |
JPS5597644A (en) | Order reexecution system |