JPS5684058A - Data transmission system - Google Patents

Data transmission system

Info

Publication number
JPS5684058A
JPS5684058A JP16124879A JP16124879A JPS5684058A JP S5684058 A JPS5684058 A JP S5684058A JP 16124879 A JP16124879 A JP 16124879A JP 16124879 A JP16124879 A JP 16124879A JP S5684058 A JPS5684058 A JP S5684058A
Authority
JP
Japan
Prior art keywords
memories
interruption
data
circuit
outputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP16124879A
Other languages
Japanese (ja)
Other versions
JPS607864B2 (en
Inventor
Tomoji Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP54161248A priority Critical patent/JPS607864B2/en
Publication of JPS5684058A publication Critical patent/JPS5684058A/en
Publication of JPS607864B2 publication Critical patent/JPS607864B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/0078—Avoidance of errors by organising the transmitted data in a format specifically designed to deal with errors, e.g. location
    • H04L1/0083—Formatting with frames or packets; Protocol or part of protocol for error control

Abstract

PURPOSE:To transmit interrupt data rapidly when an interruption is caused, by interrupting the transmission of data blocks without waiting for the transmission to end. CONSTITUTION:In a normal transmission state, switches S1-S4 are placed at side (a) and data are sent normally by transmitting circuit 12 via the 1st and 2nd memories 14 and 15 and, after being received by receiving circuit 19, outputted from an output circuit via the 3rd and 4th memories 20 and 21. Once an interruption occurs, switches S1-S4 are changed over to side (b) and interrupt data are sent from interruption transmitting circuit 30 via the 5th and 6th memories 31 and 32 and, after being received by interruption receiving circuit 33, outputted from the output circuit via the 7th and 8th memories 34 and 35. Consequently, the interrupt data can be transmitted by interrupting normally transmitted data blocks.
JP54161248A 1979-12-12 1979-12-12 data transmission equipment Expired JPS607864B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54161248A JPS607864B2 (en) 1979-12-12 1979-12-12 data transmission equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54161248A JPS607864B2 (en) 1979-12-12 1979-12-12 data transmission equipment

Publications (2)

Publication Number Publication Date
JPS5684058A true JPS5684058A (en) 1981-07-09
JPS607864B2 JPS607864B2 (en) 1985-02-27

Family

ID=15731462

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54161248A Expired JPS607864B2 (en) 1979-12-12 1979-12-12 data transmission equipment

Country Status (1)

Country Link
JP (1) JPS607864B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6227679U (en) * 1985-08-02 1987-02-19

Also Published As

Publication number Publication date
JPS607864B2 (en) 1985-02-27

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