JPS607864B2 - data transmission equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data transmission device between, for example, a CPU (central processing unit) and a terminal, and particularly relates to a transmission method when interrupting data transmission.

In the case of data transmission as described above, the data is usually composed of a plurality of data blocks, and methods for continuously transmitting these data blocks are often being explored.

A data block in such data transmission generally refers to data in an interval between a text start number (hereinafter referred to as an STX code) and a text end signal (hereinafter referred to as an ETB code).

For example, when performing parity counting, ST
Counting starts from the next character without including the X code, ends counting including the ETB code, and the result is transmitted as a block check character (hereinafter referred to as BCC) following the ETB code. FIG. 1a schematically shows the structure of the data block described above. Also, in the same figure b, this data block is A,,A2,A3・
. . , which are connected together, and such devices are generally transmitted cyclically digitally. By the way, when an interrupt request occurs during such data transmission, the transmission has conventionally been performed as follows.

That is, the STX shown in FIG. 1a is added to the interrupt data.
, ETB, BCC, etc., for example, the second data block A2 and the third data block, as shown in FIG.
The data block A3 is inserted between the data block A3 and the data block A3. Figure 2 shows this. In FIG. 2, B indicates interrupt data. FIG. 3 shows the configuration of a system for realizing the conventional data transmission method described above. The transmitting side includes an input circuit 11, a transmitting circuit 12, and a parallel-to-serial converter circuit (hereinafter referred to as a P-S converter circuit) 13. , a first memory 14, a second memory 15, and a modulation circuit 16, and the receiving side includes a demodulation circuit 17, a serial-to-parallel conversion circuit (hereinafter referred to as an S-P conversion circuit) 18, a reception circuit 19, and a third The transmitting side and the receiving side are connected by a transmission line 23.

In such a configuration, when transmitting a predetermined data block of data as shown in FIG. 1 memory 4. When the storage operation in the first memory 14 is completed,
This stored content is transferred to the second memory 15. At the same time, the input circuit 11 receives information on the next data block to be transmitted as a process input, and its contents are stored in the first memory 14. And transmitting circuit 1
2, the process input information stored in the second memory 15 is edited into one to two or more characters for each process input, and the P-S conversion circuit 13 and the modulation circuit 16
to the transmission line 23 to start data transmission. To start this data transmission, as shown in FIG. 1a, an STX code is first transmitted, and then process input information is transmitted. This process input information (
After transmitting one block worth of data, the ETB code and BC
The C code is subsequently transmitted. After transmitting one block of process input information in this way, the next block of process input information is transmitted.
The transmission operation of the block information continues. On the receiving side,
The process input information from the transmitting side transmitted via the transmission line 23 is received by the receiving circuit 19 through the demodulating circuit 17 and the S-P converting circuit 18, and the information received character by character following the STX code is received as necessary. After performing a vertical parity check, the data is converted into a process output unit and stored in the third memory 20.

If the BCC code received subsequently after receiving the ETB code is normal, the process output information stored in the third memory 201 is transferred to the fourth memory 21, and the output circuit 22 transfers the process output information stored in the third memory 201 to the fourth memory 21. The contents of the memory 21 (process output information) are output as a process. The above is a normal transmission operation. Next, the operation when an interrupt occurs during transmission as described above will be explained with reference to FIG. In Fig. 4, A, , n,... indicate data blocks,
indicates the data transmission processing time for one data block. Here, at time To, data block A
, is input to the input circuit 11, and at time T, the transmitter circuit 12
Input circuit 11, transmission circuit 12
, the receiving circuit 19, and the output circuit 22 each have a transmission delay of T time. Now, if an interrupt signal is input at time T3i, the process input of the normal data block (data block A4 in this example) that is currently being input when the interrupt signal is input is transferred from the first memory 4 to the After all the processes for transferring data to the memory 15 of No. 2 are completed, the process based on the above-mentioned interrupt signal is started.

In FIG. 4, the shaded area indicates interrupt data B. In FIG. In this way, conventionally, when an interrupt occurs at any time during a normal data transmission operation, the processing related to that interrupt is performed on the data of the data block that was being processed for normal data transmission processing when the interrupt occurred. This was done after the process was completed. Therefore, as is clear from FIG. 4, the transmission delay from the occurrence of an interrupt to the processing and process output of the interrupt is approximately 4 data blocks (4T time).

Furthermore, in general, one data block in normal transmission is a unit of several hundred characters or more, whereas one data block in interrupt transmission is a few characters. can no longer be ignored and poses a risk of developing into a serious accident. This can be a major problem, especially in systems with relatively slow transmission speeds, such as telemeters. This invention has been made in view of the above points, and when an interrupt request occurs in a device that transmits data between devices in blocks, the normal data transmission is interrupted and the interrupt data related to the interrupt request is transmitted to the highest level. It is an object of the present invention to provide a data transmission device that can prioritize transmission, minimize the time from the occurrence of an interrupt request until the arrival of interrupt data related to this interrupt request, and efficiently perform interrupt transmission in an emergency. do.

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 5 shows the configuration of a data transmission device according to the present invention, and the same parts as in FIG. 3 are given the same reference numerals, and the explanation of the overlapping parts will be omitted. The difference between FIG. 5 and FIG. 3 is that on the transmitting side, in addition to the transmitting circuit 12 shown in FIG. 3, an interrupt transmitting circuit 30 that performs a transmitting operation related to interrupts is provided as a transmitting circuit section. Selector switches S, , S2 are provided for selection, and input circuit 1
1 and the interrupt transmission circuit 30, and on the other hand, on the receiving side, the receiving circuit 1 shown in FIG.
In addition to 9, an interrupt receiving circuit 33 that performs a receiving operation regarding interrupts is provided, as well as changeover switches S3 and S4 for selecting these. 8 memory 34
, 35 were established. Note that, hereinafter, the entrusted transmission circuit 12 will be referred to as the normal transmission circuit 12, and the reception circuit 19 will be referred to as the normal reception circuit 19. The operation of the above configuration will now be described.

In the case of normal data transmission, the changeover switches S and ~S4 on the transmitting side and receiving side are both on the terminal a side, and in this case, the operation is exactly the same as the normal data transmission operation without interrupt 3 as explained in Fig. 3. Therefore, the explanation of its operation will be omitted here. The operation when an interrupt request occurs will be described below with reference to FIG. When an interrupt request occurs and an interrupt signal B3 is input at time Li, the selector switch S switches to the terminal b side, and the input circuit 11 outputs the normal data block (
Here, the process input operation of data block A4) is interrupted, and the input circuit 141 reads the process input of data related to the interrupt and stores it in the fifth memory 31.

Data 1 regarding the above-mentioned interrupt to this fifth memory 31
When the storage operation for the block is completed, the storage contents are transferred to the sixth memory 32. When this transfer operation is completed, the changeover switch S is switched back to its original state (terminal a side), and the process input operation of the normal data block (data block A4) that was interrupted due to this interrupt operation is interrupted. Continue for subsequent minutes. On the other hand, in the normal transmission circuit 12, a transmission interruption signal (hereinafter referred to as ETX code) is sent after the character of the interrupted part of the information for the data block already read by the input circuit 11.
After that, switch S2 is connected to terminal b.
switch to the side.

Then, the interrupt transmitting circuit 30 transmits the information for one block of interrupt transmission stored in the sixth memory 32.

When this transmission is completed, the selector switch S2 returns to its original state (terminal a side), and the interrupted normal transmission 1 block (
The remainder of the data block) is subsequently transmitted. on the other hand,
On the receiving side, among the data signals sent from the entrusted sending side, the ETX code is received, and after receiving this ETX code, when the BCC code is detected, the selector switch S3 is immediately switched to the terminal b side, and an interrupt is generated. The reception circuit 33 causes the seventh memory 34 to store one block of the interrupt data.

When this storage operation is completed, the stored contents are transferred to the eighth memory 35. When this transfer operation is completed, the changeover switch S3 is returned to the original state (terminal a side) and the normal data block (data block) to be subsequently received is returned.
The receiving operation for the remaining part is performed, and the information is stored in the third memory 201, and when this storage operation is completed, the stored contents are stored in the fourth memory 21. Further, when the changeover switch S3 is returned to its original state as described above, the changeover switch S4 is simultaneously switched to the terminal b side. Therefore, the output circuit 22 reads and outputs the stored contents of the eighth memory 35. When this output operation is completed, the changeover switch S4 is returned to its original state (terminal a side), and the content stored in the fourth memory 21, that is, the remaining part of the interrupted data block A4, is outputted. . FIG. 6 shows the above operation, and as is clear from FIG. 6, the interrupt data B
When this occurs, the processing of the data block (to the data block) currently being processed is interrupted, and an operation is performed in which this interrupt data B is sent with priority.

Therefore, the above interrupt data B is at the time of interrupt (ti
) until it is output from the output circuit 22 is only a time corresponding to four blocks of interrupt data B, which is a time that can be almost ignored. By the way, in order to realize the above-described system, a circuit as shown in FIG. 7 is required on the receiving side.

The circuit shown in FIG. 7 is composed of flip-flops FF, FF2 and AND circuits AND, , AND2. This is for transmission. However, if the items for normal transmission and the items for interrupt transmission are completely separated, this circuit is unnecessary. However, in the case of a telemeter, etc., all items that need to be transmitted are transmitted in a fixed cycle, and the receiving side detects whether or not they are received at fixed intervals.
If the data cannot be received even after a certain period of time has elapsed, it is generally assumed that the data is missing. Therefore, since the interrupt transmission is a data transmission that interrupts a data block of normal transmission, the process input input by the input circuit 11 is not sequentially output as a process output. Therefore, the process input information that is read later is outputted in the process before the process input information of the same point that is captured earlier. Therefore, either the information contained in the data block of normal transmission received after the information transmitted with an interrupt is not output to the process, or the information received during the interrupt transmission is treated as if it had been received normally, and this value is changed. A process output method is adopted. FIG. 8 is a diagram showing the flow of operation according to this method. Figure 8a shows the reception cycle of a specific word, Figure 8b shows the normal reception cycle, and Figure 8c shows the reception cycle of a specific word.
d is the set Q output of flip-flop FF, d is the set Q output of flip-flop FF2, f is the process output, and f is the process output. mosquito,
Or output the same value as the previous process output value. In the above embodiments, interrupt transmission has been described with respect to an operation in which a data block of normal transmission is interrupted and transmitted, but it is not always necessary to interrupt and transmit a data block of normal transmission.

Depending on the timing, it may occur between data blocks of normal transmission. In such a case, the input and transmission operations on the transmitting side are
The operation shown in the figure is performed, but since the ETX code cannot be detected in the reception and output operations on the receiving side, the fourth
The process will be as shown in the figure. Therefore, if a code corresponding to the STX code during normal transmission, such as an ETX code, is provided as the transmission start text code, and the data block for normal transmission and the data block for interrupt transmission are separated by the text code, the receiving circuit Now, with the conventional ETX code, not only can switch S3 be switched, but also when an ETX' code is received, interrupt reception can be performed by switching switch S3. As explained above, according to the present invention, there is no interruption between devices.

In devices that transmit data in units of blocks, a normal transmitting section, an interrupt transmitting section, a normal receiving section, and an interrupt receiving section are provided on the transmitting side and the receiving side, and these transmitting sections and receiving sections are connected to each other by a switching means to handle interrupt requests. When this occurs, normal data transmission is interrupted and the interrupt data related to the interrupt request is transmitted with the highest priority through the interrupt transmitting section and the interrupt receiving section. It is possible to minimize the time it takes for data to arrive, to efficiently perform interrupt transmission in an emergency, and to provide a data transmission device that is particularly effective in systems with relatively slow transmission speeds, such as telemeters.

[Brief explanation of drawings]

Figure 1a is a diagram showing the configuration of a data block, Figure 1b
Figure 2 is a diagram showing an example of a data configuration made up of multiple data blocks; Figure 2 is a diagram showing an example of a data configuration obtained by inserting interrupt data into the data in Figure 1b, and Figure 3 is a diagram showing a conventional FIG. 4 is a block diagram showing an example of a configuration of a data transmission system; FIG. 4 is a timing chart showing the operation of a conventional data transmission system; FIG. 5 is a configuration diagram showing an embodiment of a data transmission device according to the present invention; The figure is a timing chart showing the operation of the same embodiment, FIG. 7 is a block diagram showing the circuit required on the receiving side in the same embodiment, and FIG. 8 is a timing chart showing the operation of the circuit of FIG. 11... Input circuit, 12... Normal transmission circuit, I4... First memory, 15... Second memory,
19... Normal receiving circuit, 20... Third memory, 21... Fourth memory, 22...
・Output circuit, 30... Interrupt transmission circuit, 31.
...Fifth memory, 32...Sixth memory, 33...Interrupt receiving circuit, 34...Seventh memory, 35...Eighth memory, S ,~S4...
・Choice switch. Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8

Claims (1)

[Claims] 1. In a data transmission device that transmits data composed of a plurality of blocks, there is a normal transmitter that transmits the data from an input circuit that takes in the data in normal times, and an interrupt that transmits interrupt data from the input circuit. a transmitting side comprising a transmitting section, and a transmitting side switching means that is switched in response to generation of an interrupt request to send data from the input circuit to the interrupt transmitting section and transmit interrupt data from the interrupt transmitting section; a normal receiving section that receives data normally sent from the transmitting side; an interrupt receiving section that receives interrupt data from the transmitting side; and a signal indicating the interrupt data based on the data from the transmitting side. receiving side switching means that switches when the normal transmitting side is detected and sends the interrupt data from the transmitting side to the interrupt receiving section, and sends the interrupt data from the interrupt receiving section to the output circuit. When an interrupt request occurs, the transmitting side switching means switches to interrupt the normal data and transmit the interrupt data through the interrupt transmitting unit, and the receiving side A data transmission device, characterized in that the interrupt data is received by the interrupt receiving section by the switching means, and then the interrupted normal data is transmitted.