JPS5683949A - Assembling of semiconductor device - Google Patents

Assembling of semiconductor device

Info

Publication number
JPS5683949A
JPS5683949A JP16104079A JP16104079A JPS5683949A JP S5683949 A JPS5683949 A JP S5683949A JP 16104079 A JP16104079 A JP 16104079A JP 16104079 A JP16104079 A JP 16104079A JP S5683949 A JPS5683949 A JP S5683949A
Authority
JP
Japan
Prior art keywords
carrier
leads
tip
fixed
endless
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16104079A
Other languages
Japanese (ja)
Inventor
Rikuro Sono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP16104079A priority Critical patent/JPS5683949A/en
Publication of JPS5683949A publication Critical patent/JPS5683949A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item

Abstract

PURPOSE:To provide a convinient automatic assembly by a method wherein lead lines of a tip carrier are stamped from the endless metal plate, formed, and the leads are not separated from the metal plate during connection of the lines to prevent an electrostatic decay, then taken up. CONSTITUTION:Comblike leads 4 are made at the endless belt 1 of Koval plated with copper. Tip carrier 5 is attached, a center of the tip carrier is aligned with that of the opening 2, and outer terminal 6 is fixed to the leads 4 and the bottom surface of the carrier 5. Seimiconductor element 9 is fixed to the carrier 5, and each of the terminals is connected to the inner terminal 8 of the carrier. At this time, all the outer terminals 6 of the tip carrier 5 are shortcircuited through metalic band 1, so that the semiconductor element 9 is not destroyed by static electricity. Thereafter, the assembly is air sealed by the cap 10 and the leads 4 are cut to a suitable length for its use. In this way, if a large number of tip carriers are fixed to the endless metalic tape with a proper spacing therebetween, an automatic assembly of the semiconductor device may easily be made, the carrier may be taken up or wound up so as to be stored.
JP16104079A 1979-12-12 1979-12-12 Assembling of semiconductor device Pending JPS5683949A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16104079A JPS5683949A (en) 1979-12-12 1979-12-12 Assembling of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16104079A JPS5683949A (en) 1979-12-12 1979-12-12 Assembling of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5683949A true JPS5683949A (en) 1981-07-08

Family

ID=15727446

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16104079A Pending JPS5683949A (en) 1979-12-12 1979-12-12 Assembling of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5683949A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5984556A (en) * 1982-11-08 1984-05-16 Hitachi Micro Comput Eng Ltd Semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5489575A (en) * 1977-12-27 1979-07-16 Fujitsu Ltd Manufacture for semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5489575A (en) * 1977-12-27 1979-07-16 Fujitsu Ltd Manufacture for semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5984556A (en) * 1982-11-08 1984-05-16 Hitachi Micro Comput Eng Ltd Semiconductor device

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