JPS5674891A - Control system of storage device - Google Patents
Control system of storage deviceInfo
- Publication number
- JPS5674891A JPS5674891A JP14973579A JP14973579A JPS5674891A JP S5674891 A JPS5674891 A JP S5674891A JP 14973579 A JP14973579 A JP 14973579A JP 14973579 A JP14973579 A JP 14973579A JP S5674891 A JPS5674891 A JP S5674891A
- Authority
- JP
- Japan
- Prior art keywords
- address
- refresh
- period
- lower bit
- fixed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Complex Calculations (AREA)
Abstract
PURPOSE:To increase the operational speed during the memory by the address updated with a fixed sequence and a fixed period by using the lower bit of an address also as a refresh address. CONSTITUTION:Address counter 14 updates addresses with a fixed sequence and a fixed period by address control signal CNT from operation control part 11. When control part 11 discriminates the first period, selecting circuit 15 selects an address from counter 14 and outputs the lower bit of the selected address as a line address and the upper bit as a row address to storage devices 121 to 122. During the 1st period, refreshing by refresh circuit 13 is inhibited and the lower bit is used as a refresh address. Thus, the delay of operation time caused by a refresh cycle is prevented, making it possible to increase operational speed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14973579A JPS5674891A (en) | 1979-11-19 | 1979-11-19 | Control system of storage device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14973579A JPS5674891A (en) | 1979-11-19 | 1979-11-19 | Control system of storage device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5674891A true JPS5674891A (en) | 1981-06-20 |
Family
ID=15481659
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14973579A Pending JPS5674891A (en) | 1979-11-19 | 1979-11-19 | Control system of storage device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5674891A (en) |
-
1979
- 1979-11-19 JP JP14973579A patent/JPS5674891A/en active Pending
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