JPS5671926A - Chip carrier - Google Patents

Chip carrier

Info

Publication number
JPS5671926A
JPS5671926A JP14847679A JP14847679A JPS5671926A JP S5671926 A JPS5671926 A JP S5671926A JP 14847679 A JP14847679 A JP 14847679A JP 14847679 A JP14847679 A JP 14847679A JP S5671926 A JPS5671926 A JP S5671926A
Authority
JP
Japan
Prior art keywords
carriers
pin members
positioning
printed circuit
electrical connections
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14847679A
Other languages
Japanese (ja)
Inventor
Takeshi Taketomi
Shizuhiro Sakaniwa
Hiroyuki Mori
Takeshi Murayama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14847679A priority Critical patent/JPS5671926A/en
Publication of JPS5671926A publication Critical patent/JPS5671926A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)

Abstract

PURPOSE:To minimize a package loss by providing pin members at the sides of chip carriers wherein the pin members can be inserted in the predetermined holes of a substrate for fixing the carriers and have functions of positioning or misinsertion or electrical connections to a power supply and other low-speed operating elements. CONSTITUTION:Metallized conductors 3a, 3d premitting a connection by using conductor patterns 5 provided on a printed circuit substrate 4 and solder 11 are provided at the sides of a case 2 composing of chip carriers 1 and the pin members 14 are also fixed to the corner sections of one side through the metallized layers 15 while thrusting out downward. Next, the carriers 1 are placed on the printed circuit substrate 4 packing the carriers 1 and the pin members 14 are inserted in through holes 6 penetrating the patterns 5. In this way, the pin members 14 are provided on the carriers and the carriers having small inductance and electrostatic capacity will be obtained by using the pin members 14 for positioning and electrical connections as well.
JP14847679A 1979-11-16 1979-11-16 Chip carrier Pending JPS5671926A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14847679A JPS5671926A (en) 1979-11-16 1979-11-16 Chip carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14847679A JPS5671926A (en) 1979-11-16 1979-11-16 Chip carrier

Publications (1)

Publication Number Publication Date
JPS5671926A true JPS5671926A (en) 1981-06-15

Family

ID=15453599

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14847679A Pending JPS5671926A (en) 1979-11-16 1979-11-16 Chip carrier

Country Status (1)

Country Link
JP (1) JPS5671926A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5146308A (en) * 1990-10-05 1992-09-08 Micron Technology, Inc. Semiconductor package utilizing edge connected semiconductor dice
US5306948A (en) * 1991-10-03 1994-04-26 Hitachi, Ltd. Semiconductor device and semiconductor module having auxiliary high power supplying terminals
US5616958A (en) * 1995-01-25 1997-04-01 International Business Machines Corporation Electronic package

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5146308A (en) * 1990-10-05 1992-09-08 Micron Technology, Inc. Semiconductor package utilizing edge connected semiconductor dice
US5306948A (en) * 1991-10-03 1994-04-26 Hitachi, Ltd. Semiconductor device and semiconductor module having auxiliary high power supplying terminals
US5616958A (en) * 1995-01-25 1997-04-01 International Business Machines Corporation Electronic package
US5728606A (en) * 1995-01-25 1998-03-17 International Business Machines Corporation Electronic Package

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