JPS567154A - Double system - Google Patents

Double system

Info

Publication number
JPS567154A
JPS567154A JP8015379A JP8015379A JPS567154A JP S567154 A JPS567154 A JP S567154A JP 8015379 A JP8015379 A JP 8015379A JP 8015379 A JP8015379 A JP 8015379A JP S567154 A JPS567154 A JP S567154A
Authority
JP
Japan
Prior art keywords
rank
diagnosis
computer
fault
computers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8015379A
Other languages
Japanese (ja)
Other versions
JPS6236241B2 (en
Inventor
Eiji Toyama
Akira Sugano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8015379A priority Critical patent/JPS567154A/en
Publication of JPS567154A publication Critical patent/JPS567154A/en
Publication of JPS6236241B2 publication Critical patent/JPS6236241B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Safety Devices In Control Systems (AREA)

Abstract

PURPOSE: To realize the switching between the main system and the stand-by system in a highly accurate and assured way, by giving both the self-diagnosis function and the mutual diagnosis function to two units of the higher-rank computers each plus the function to give the diagnosis for the higher-rank computers to the lower-rank computer and then combining these three diagnoses.
CONSTITUTION: Main system 10-A and stand-by system 10-B of the higher-rank computer receive the same signal through system bus 1 and then perform the same operation. Thus the control command is given from the main-system computer, and the both systmes possess self-diagnosis means SDA and SDB plus mutual diagnosis means MDA and MDB which give the diagnosis to the fault of the other side to each other. Lower-rank computers 20-IW20-N also possess self- diagnosis means SD1WSDn plus fault detecting means MD1WMDn which check the rationality of the control order given from the higher-rank computer to detect the fault of the higher-rank computer. When the fault is detected through these diagnosis means and fault detecting means, the detection signal is sent to switching decision circuit 30. At circuit 30, the fixed weighting is given to each detection signal and then the addition is carried out. When the addition output reaches the fixed weight, the control order is switched to the stand-by system from the main system through the higher-rank computer.
COPYRIGHT: (C)1981,JPO&Japio
JP8015379A 1979-06-27 1979-06-27 Double system Granted JPS567154A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8015379A JPS567154A (en) 1979-06-27 1979-06-27 Double system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8015379A JPS567154A (en) 1979-06-27 1979-06-27 Double system

Publications (2)

Publication Number Publication Date
JPS567154A true JPS567154A (en) 1981-01-24
JPS6236241B2 JPS6236241B2 (en) 1987-08-06

Family

ID=13710342

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8015379A Granted JPS567154A (en) 1979-06-27 1979-06-27 Double system

Country Status (1)

Country Link
JP (1) JPS567154A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS582901A (en) * 1981-06-30 1983-01-08 Nec Home Electronics Ltd Reset signal generating circuit
JPS58134359A (en) * 1982-02-05 1983-08-10 Hitachi Ltd Bus switching device
JPS62204346A (en) * 1986-03-05 1987-09-09 Hitachi Ltd Duplex system switching system
JPH01295338A (en) * 1987-12-25 1989-11-29 Fujitsu Ltd On switch control system for separation display flag of duplex system
JP2008299369A (en) * 2007-05-29 2008-12-11 Nomura Research Institute Ltd Cluster system, computer, and failure coping method
JP2011103071A (en) * 2009-11-11 2011-05-26 Hitachi Ltd Multiplexing control device
WO2022024634A1 (en) * 2020-07-31 2022-02-03 日立Astemo株式会社 Computing device and vehicle control device

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008060713A (en) * 2006-08-29 2008-03-13 Fuji Xerox Co Ltd Information processing apparatus and program

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS582901A (en) * 1981-06-30 1983-01-08 Nec Home Electronics Ltd Reset signal generating circuit
JPS58134359A (en) * 1982-02-05 1983-08-10 Hitachi Ltd Bus switching device
JPS6330660B2 (en) * 1982-02-05 1988-06-20 Hitachi Ltd
JPS62204346A (en) * 1986-03-05 1987-09-09 Hitachi Ltd Duplex system switching system
JPH01295338A (en) * 1987-12-25 1989-11-29 Fujitsu Ltd On switch control system for separation display flag of duplex system
JP2008299369A (en) * 2007-05-29 2008-12-11 Nomura Research Institute Ltd Cluster system, computer, and failure coping method
JP2011103071A (en) * 2009-11-11 2011-05-26 Hitachi Ltd Multiplexing control device
WO2022024634A1 (en) * 2020-07-31 2022-02-03 日立Astemo株式会社 Computing device and vehicle control device
JP2022026647A (en) * 2020-07-31 2022-02-10 日立Astemo株式会社 Arithmetic logic unit and vehicle control unit

Also Published As

Publication number Publication date
JPS6236241B2 (en) 1987-08-06

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