JPS5668993A - Shift register - Google Patents
Shift registerInfo
- Publication number
- JPS5668993A JPS5668993A JP14483879A JP14483879A JPS5668993A JP S5668993 A JPS5668993 A JP S5668993A JP 14483879 A JP14483879 A JP 14483879A JP 14483879 A JP14483879 A JP 14483879A JP S5668993 A JPS5668993 A JP S5668993A
- Authority
- JP
- Japan
- Prior art keywords
- address
- contents
- data
- shift
- ram20
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/38—Digital stores in which the information is moved stepwise, e.g. shift registers two-dimensional, e.g. horizontal and vertical shift registers
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Executing Machine-Instructions (AREA)
- Shift Register Type Memory (AREA)
Abstract
PURPOSE:To eliminate the operation of the modulo (n) for the output access and thus realize a high-speed operation for the shift register which performs a shift by an address operation and via a large-capacity RAM, by providing the K-bit counter as a pointer. CONSTITUTION:The data to be shifted to the large-capacity RAM20 of 2K words is written through the latch circuit 21 and in synchronization with the clock CLK. The address of this instant is formed by adding through the adder 24 and with K bits the contents of the K-bit counter 23 which performs a count-down to the contents obtained by latching the shift amount data through the latch circuit 22 and by the address strobe signal ADRSTB. The circuit 22 is cleared CLR with every clock, and the shift amount data is latched only when the shifted data is read out. Then the contents of the counter 23 at that moment and the added contents form the address which is read out of the RAM20.
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14483879A JPS5668993A (en) | 1979-11-08 | 1979-11-08 | Shift register |
US06/204,923 US4393482A (en) | 1979-11-08 | 1980-11-07 | Shift register |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14483879A JPS5668993A (en) | 1979-11-08 | 1979-11-08 | Shift register |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5668993A true JPS5668993A (en) | 1981-06-09 |
Family
ID=15371603
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14483879A Pending JPS5668993A (en) | 1979-11-08 | 1979-11-08 | Shift register |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5668993A (en) |
-
1979
- 1979-11-08 JP JP14483879A patent/JPS5668993A/en active Pending
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