JPS5665246A - Digital adder - Google Patents

Digital adder

Info

Publication number
JPS5665246A
JPS5665246A JP14133879A JP14133879A JPS5665246A JP S5665246 A JPS5665246 A JP S5665246A JP 14133879 A JP14133879 A JP 14133879A JP 14133879 A JP14133879 A JP 14133879A JP S5665246 A JPS5665246 A JP S5665246A
Authority
JP
Japan
Prior art keywords
addition
adder
data
adders
carry
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14133879A
Other languages
Japanese (ja)
Inventor
Makoto Onishi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14133879A priority Critical patent/JPS5665246A/en
Publication of JPS5665246A publication Critical patent/JPS5665246A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To obtain an addition data at a higher rate than a clock rate for addition by use of a series adder, by executing addition of a data and addition of a carry output generated by addition, by means of different adders and shifting the time.
CONSTITUTION: The adder 13 and the D type FF15 puls the adder 14 and the D type FF16 constitute the series adders respectively, and FFs 15, 16 constitute the carry circuits for the respective adders 13, 15. And a carry signal generated in the period Ti+1 by addition of the data Di and Di+1(i=1...7) by the adder 13 is added to the total sum of the previous carry outputs by the adder 14 in the next period Ti+2. In this way, an addition data can be obtained by use of a series adder at a higher rate than a clock rate for addition, by executing addition of a data and addition of a carry output generated by addition, by means of different adders and also shifting the time.
COPYRIGHT: (C)1981,JPO&Japio
JP14133879A 1979-11-02 1979-11-02 Digital adder Pending JPS5665246A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14133879A JPS5665246A (en) 1979-11-02 1979-11-02 Digital adder

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14133879A JPS5665246A (en) 1979-11-02 1979-11-02 Digital adder

Publications (1)

Publication Number Publication Date
JPS5665246A true JPS5665246A (en) 1981-06-02

Family

ID=15289624

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14133879A Pending JPS5665246A (en) 1979-11-02 1979-11-02 Digital adder

Country Status (1)

Country Link
JP (1) JPS5665246A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008527274A (en) * 2005-01-14 2008-07-24 イートン コーポレーション Electrically operated differential fixing device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008527274A (en) * 2005-01-14 2008-07-24 イートン コーポレーション Electrically operated differential fixing device
JP4894017B2 (en) * 2005-01-14 2012-03-07 イートン コーポレーション Electrically operated differential fixing device

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