JPS5661851A - Pulse receiving circuit - Google Patents

Pulse receiving circuit

Info

Publication number
JPS5661851A
JPS5661851A JP13703479A JP13703479A JPS5661851A JP S5661851 A JPS5661851 A JP S5661851A JP 13703479 A JP13703479 A JP 13703479A JP 13703479 A JP13703479 A JP 13703479A JP S5661851 A JPS5661851 A JP S5661851A
Authority
JP
Japan
Prior art keywords
clock
phase
phii
information signal
read
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13703479A
Other languages
Japanese (ja)
Other versions
JPS596542B2 (en
Inventor
Seiichiro Kozuka
Toshinori Tsuboi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP54137034A priority Critical patent/JPS596542B2/en
Publication of JPS5661851A publication Critical patent/JPS5661851A/en
Publication of JPS596542B2 publication Critical patent/JPS596542B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To ensure the reception of the information signal with the correct clock, by selecting automatically the clock phase which can regenerate the information signal without error out of the n-phase clocks generated from the network synchronous oscillator. CONSTITUTION:The appropriate phase phii is selected among the n-phase clocks in the initial state, and the information signal is read by the selected clock of phii and through the FF17. On the other hand, the information signal is read in the FF18 with the clock obtained by giving a slight delay to the clock of phii. Then a comparison is given between the both signals through the FF19 and 20, and the coincidence is decided for these outputs through the exclusive logic sum circuit 22. Thus the read-in of the phase phii is continued in case a coicidence is obtained; while the new phase phij is selected through the selector 13 and the counter 14 when no coincidence is obtained. In this way, the information can be received with the correct clock.
JP54137034A 1979-10-25 1979-10-25 Pulse receiver circuit Expired JPS596542B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54137034A JPS596542B2 (en) 1979-10-25 1979-10-25 Pulse receiver circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54137034A JPS596542B2 (en) 1979-10-25 1979-10-25 Pulse receiver circuit

Publications (2)

Publication Number Publication Date
JPS5661851A true JPS5661851A (en) 1981-05-27
JPS596542B2 JPS596542B2 (en) 1984-02-13

Family

ID=15189295

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54137034A Expired JPS596542B2 (en) 1979-10-25 1979-10-25 Pulse receiver circuit

Country Status (1)

Country Link
JP (1) JPS596542B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0141946A2 (en) * 1983-09-13 1985-05-22 ANT Nachrichtentechnik GmbH Circuit arrangement for synchronising the transitions of binary signals with a clock
JPS60244130A (en) * 1984-05-18 1985-12-04 Hitachi Ltd Detection system of identified phase
FR2604043A1 (en) * 1986-09-17 1988-03-18 Cit Alcatel DEVICE FOR RECALING ONE OR MORE BINARY DATA TRAINS IN IDENTICAL OR SUB-MULTIPLY RATES ON A SYNCHRONOUS CLOCK REFERENCE SIGNAL
JPH01151333A (en) * 1987-12-08 1989-06-14 Nec Corp Automatic phase adjusting system for data signal and clock signal
JPH0353629A (en) * 1989-07-21 1991-03-07 Hitachi Ltd Bit phase synchronizing circuit and data transmission equipment

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0141946A2 (en) * 1983-09-13 1985-05-22 ANT Nachrichtentechnik GmbH Circuit arrangement for synchronising the transitions of binary signals with a clock
JPS60244130A (en) * 1984-05-18 1985-12-04 Hitachi Ltd Detection system of identified phase
FR2604043A1 (en) * 1986-09-17 1988-03-18 Cit Alcatel DEVICE FOR RECALING ONE OR MORE BINARY DATA TRAINS IN IDENTICAL OR SUB-MULTIPLY RATES ON A SYNCHRONOUS CLOCK REFERENCE SIGNAL
US4780889A (en) * 1986-09-17 1988-10-25 Alcatel Cit Device for relocking one or a number of identical or submultiple binary data signal trains on a synchronous reference clock signal
JPH01151333A (en) * 1987-12-08 1989-06-14 Nec Corp Automatic phase adjusting system for data signal and clock signal
JPH0353629A (en) * 1989-07-21 1991-03-07 Hitachi Ltd Bit phase synchronizing circuit and data transmission equipment

Also Published As

Publication number Publication date
JPS596542B2 (en) 1984-02-13

Similar Documents

Publication Publication Date Title
US3755748A (en) Digital phase shifter/synchronizer and method of shifting
CA2048514A1 (en) Synchronous processor unit with interconnected, separately clocked processor sections
JPS5720052A (en) Input data synchronizing circuit
CA1090888A (en) Data buffer retiming circuit
EP0102662A3 (en) Non-pll concurrent carrier and clock synchronization
JPS5661851A (en) Pulse receiving circuit
JPS5360150A (en) Instantaneous leading-in system for digital phase lock loop
EP0225512B1 (en) Digital free-running clock synchronizer
EP0240232A3 (en) Digital phase lock loop
JPS55134424A (en) Bit phase synchronizing circuit
JPS558166A (en) Data transmission system
JPS56160175A (en) Synchronous signal generator
JPS558103A (en) Reproducing system of timing information
JPS5614727A (en) Phase comparator of digital pll circuit
JPS54124611A (en) Communication unit
JPS53144217A (en) Smapling clock reproducer
SU873203A1 (en) Radiotechnical clock station
JPS54100243A (en) Redundant multi-phase clock generator circuit
JPH04145566A (en) Serial transferring circuit
JPS55135448A (en) Extracting system for manchester code clock
JPS54148413A (en) Reproduction system for timing information
JPS5454563A (en) Bit phase synchronous circuit
JPS5710566A (en) Decoding circuit
JPS5758444A (en) Clock extracting system in dipulse code composite circuit
JPS52131443A (en) Phase synchronization circuit