JPS5657340A - Signal receiver - Google Patents

Signal receiver

Info

Publication number
JPS5657340A
JPS5657340A JP13457579A JP13457579A JPS5657340A JP S5657340 A JPS5657340 A JP S5657340A JP 13457579 A JP13457579 A JP 13457579A JP 13457579 A JP13457579 A JP 13457579A JP S5657340 A JPS5657340 A JP S5657340A
Authority
JP
Japan
Prior art keywords
signal
circuit
resistances
plus
receiver
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13457579A
Other languages
Japanese (ja)
Inventor
Yasuhiro Okada
Kenzo Tanabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP13457579A priority Critical patent/JPS5657340A/en
Publication of JPS5657340A publication Critical patent/JPS5657340A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03G—CONTROL OF AMPLIFICATION
    • H03G5/00—Tone control or bandwidth control in amplifiers
    • H03G5/16—Automatic control
    • H03G5/18—Automatic control in untuned amplifiers
    • H03G5/22—Automatic control in untuned amplifiers having semiconductor devices

Landscapes

  • Noise Elimination (AREA)

Abstract

PURPOSE:To eliminate the deterioration of S/N for the demodulation signal with the weak input signal by varying the frequency characteristics of the aural frequency amplifying circuit in a signal receiver in accordance with the input level of the receiver, thus obtaining a signal receiver suited to an integrated circuit. CONSTITUTION:The following terminals are provided to the frequency characteristics varying circuit of a signal receiver: the control signal input terminal 10 which applies the output signal supplied from the carrier level detector; the signal input terminal 11 which applies the output signal from the signal demodulator; the DC power connection terminal 12; and the signal output terminal 13 each. Then a double balanced circuit consists of the transistors TRQ4-Q9 plus resistances R8 and R9. And in case the signal voltage is applied only to the base side of the TRQ8, the gain is controlled by giving a control to the voltage between the TRQ5 and Q6. Thus the function of a gain amplifier can be obtained. The bias current of the balanced circuit is decided by the resistances R10 and R11 plus TRQ10 of the circuit, and the function of a current Miller is secured by the TRQ10 to the TRQ8 and Q9. Furthermore, a differential amplifier is formed with the TRQ1-Q3 plus the resistances R1-R7 to facilitate an easy formation of an IC.
JP13457579A 1979-10-17 1979-10-17 Signal receiver Pending JPS5657340A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13457579A JPS5657340A (en) 1979-10-17 1979-10-17 Signal receiver

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13457579A JPS5657340A (en) 1979-10-17 1979-10-17 Signal receiver

Publications (1)

Publication Number Publication Date
JPS5657340A true JPS5657340A (en) 1981-05-19

Family

ID=15131551

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13457579A Pending JPS5657340A (en) 1979-10-17 1979-10-17 Signal receiver

Country Status (1)

Country Link
JP (1) JPS5657340A (en)

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