JPS5652427A - Synchronous logical unit - Google Patents

Abstract

PURPOSE: To make it possible to secure synchronism against various fluctuations, by applying a reference clock pulse to the logical block through the delay circuit, and controlling a delay time of the delay circuit in accordance with a phase difference signal of each logical block.

CONSTITUTION: A reference clock which has been generated by the clock generating circuit 101 is supplied to the delay circuits 102, 103, and is distributed to the logical blocks 104, 105 as a delay clock. Phase detecting clocks which have been taken out by the gates 107, 109 of the blocks 104, 105 are input to the phase detecting circuits 110, 111, respectively, and are compared with the reference clock from the circuit 101. The circuits 110, 111 detect a phase difference signal whose level becomes large as the phase difference of two clocks becomes large, and control a delay time of the circuits 102, 103 by this phase difference signal. The circuits 102, 103 are controlled so that the shorter the phase delay time can be made, the larger the phase difference signal is. In this way, synchronism can be secured without readjusting against fluctuations such as temperature, the supply voltage, etc., and without increasing the clock cycle.

COPYRIGHT: (C)1981,JPO&Japio