JPS5652427A - Synchronous logical unit - Google Patents
Synchronous logical unitInfo
- Publication number
- JPS5652427A JPS5652427A JP12761779A JP12761779A JPS5652427A JP S5652427 A JPS5652427 A JP S5652427A JP 12761779 A JP12761779 A JP 12761779A JP 12761779 A JP12761779 A JP 12761779A JP S5652427 A JPS5652427 A JP S5652427A
- Authority
- JP
- Japan
- Prior art keywords
- circuits
- phase difference
- delay
- difference signal
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Logic Circuits (AREA)
Abstract
PURPOSE: To make it possible to secure synchronism against various fluctuations, by applying a reference clock pulse to the logical block through the delay circuit, and controlling a delay time of the delay circuit in accordance with a phase difference signal of each logical block.
CONSTITUTION: A reference clock which has been generated by the clock generating circuit 101 is supplied to the delay circuits 102, 103, and is distributed to the logical blocks 104, 105 as a delay clock. Phase detecting clocks which have been taken out by the gates 107, 109 of the blocks 104, 105 are input to the phase detecting circuits 110, 111, respectively, and are compared with the reference clock from the circuit 101. The circuits 110, 111 detect a phase difference signal whose level becomes large as the phase difference of two clocks becomes large, and control a delay time of the circuits 102, 103 by this phase difference signal. The circuits 102, 103 are controlled so that the shorter the phase delay time can be made, the larger the phase difference signal is. In this way, synchronism can be secured without readjusting against fluctuations such as temperature, the supply voltage, etc., and without increasing the clock cycle.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12761779A JPS5652427A (en) | 1979-10-02 | 1979-10-02 | Synchronous logical unit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12761779A JPS5652427A (en) | 1979-10-02 | 1979-10-02 | Synchronous logical unit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5652427A true JPS5652427A (en) | 1981-05-11 |
Family
ID=14964510
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12761779A Pending JPS5652427A (en) | 1979-10-02 | 1979-10-02 | Synchronous logical unit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5652427A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60116224A (en) * | 1983-11-29 | 1985-06-22 | Fujitsu Ltd | Semiconductor integrated circuit device |
-
1979
- 1979-10-02 JP JP12761779A patent/JPS5652427A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS60116224A (en) * | 1983-11-29 | 1985-06-22 | Fujitsu Ltd | Semiconductor integrated circuit device |
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