JPS5648741A - Bus control system - Google Patents
Bus control systemInfo
- Publication number
- JPS5648741A JPS5648741A JP12455179A JP12455179A JPS5648741A JP S5648741 A JPS5648741 A JP S5648741A JP 12455179 A JP12455179 A JP 12455179A JP 12455179 A JP12455179 A JP 12455179A JP S5648741 A JPS5648741 A JP S5648741A
- Authority
- JP
- Japan
- Prior art keywords
- bus
- transmission frame
- frame length
- data
- buses
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/42—Loop networks
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Small-Scale Networks (AREA)
Abstract
PURPOSE:To shorten transfer time and to reduce the volume of information transmission by transferring data by selecting one of common buses, differing in transfer frame length, according to data length. CONSTITUTION:To (n) common buses #1-#n, (m) subsystems 5 are connected through corresponding bus interface parts 6. Bus interface part 6 selects one of common buses #1-#n to transmit and receive information to and from connected subsystems 5. Buses 4 differ in transmission frame length; #1 common bus 4 has the longest transmission frame length for long data, #2 bus 4 a shorter transmission frame length, and so on up to #n bus 4 the shortest transmission frame lengthe for the longest data. When one subsystem 5 is to transfer information to another subsystem 5, bus interface part 6 selects bus 4 having the best transmission frame length to manage with a small number of padding characters, so that the processing performance can be improved.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12455179A JPS5648741A (en) | 1979-09-27 | 1979-09-27 | Bus control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12455179A JPS5648741A (en) | 1979-09-27 | 1979-09-27 | Bus control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5648741A true JPS5648741A (en) | 1981-05-02 |
Family
ID=14888272
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12455179A Pending JPS5648741A (en) | 1979-09-27 | 1979-09-27 | Bus control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5648741A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4845706A (en) * | 1984-06-29 | 1989-07-04 | Franaszek Peter A | Switch configured network |
-
1979
- 1979-09-27 JP JP12455179A patent/JPS5648741A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4845706A (en) * | 1984-06-29 | 1989-07-04 | Franaszek Peter A | Switch configured network |
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