JPS5647980A - Address converter - Google Patents

Address converter

Info

Publication number
JPS5647980A
JPS5647980A JP12137779A JP12137779A JPS5647980A JP S5647980 A JPS5647980 A JP S5647980A JP 12137779 A JP12137779 A JP 12137779A JP 12137779 A JP12137779 A JP 12137779A JP S5647980 A JPS5647980 A JP S5647980A
Authority
JP
Japan
Prior art keywords
address
space name
logic
hash bit
adg
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12137779A
Other languages
Japanese (ja)
Inventor
Akito Otake
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12137779A priority Critical patent/JPS5647980A/en
Publication of JPS5647980A publication Critical patent/JPS5647980A/en
Pending legal-status Critical Current

Links

Landscapes

  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE: To increase the efficiency of utilization of an address conversion buffer by suppressing a hash bit at one part of an address space name only when a logic address indicates shared space in a virtual memory data processing system.
CONSTITUTION: Virtual address register LA is provided with areas for segment number SN, page number PN and displacement D in a page, register JP holds an address space name during current execution, and address generating circuit ADG uses number SN of LA and the hash bit of JP to attain access to address conversion buffer TLB. Then, TLB includes information on the logic address, actual address, address space name, etc., and has compartments 0 and 1 and detecting circuit ADM compares addresses of a couple of entries addressed by the logic address from LA, address space name from JP and ADG to the space name and sends out a corresponding actual address when the comparison result shows identity. Then, a fixed hash bit is suppressed and outputted at the time of a shared segment.
COPYRIGHT: (C)1981,JPO&Japio
JP12137779A 1979-09-20 1979-09-20 Address converter Pending JPS5647980A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12137779A JPS5647980A (en) 1979-09-20 1979-09-20 Address converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12137779A JPS5647980A (en) 1979-09-20 1979-09-20 Address converter

Publications (1)

Publication Number Publication Date
JPS5647980A true JPS5647980A (en) 1981-04-30

Family

ID=14809715

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12137779A Pending JPS5647980A (en) 1979-09-20 1979-09-20 Address converter

Country Status (1)

Country Link
JP (1) JPS5647980A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61269753A (en) * 1985-05-24 1986-11-29 Hitachi Ltd Address conversion device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61269753A (en) * 1985-05-24 1986-11-29 Hitachi Ltd Address conversion device

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