JPS5634114A - Data separation circuit - Google Patents

Data separation circuit

Info

Publication number
JPS5634114A
JPS5634114A JP11004879A JP11004879A JPS5634114A JP S5634114 A JPS5634114 A JP S5634114A JP 11004879 A JP11004879 A JP 11004879A JP 11004879 A JP11004879 A JP 11004879A JP S5634114 A JPS5634114 A JP S5634114A
Authority
JP
Japan
Prior art keywords
signal
circuit
data
separation circuit
reproducing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11004879A
Other languages
Japanese (ja)
Inventor
Yoshitaka Katayama
Daiki Nabeshima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP11004879A priority Critical patent/JPS5634114A/en
Publication of JPS5634114A publication Critical patent/JPS5634114A/en
Pending legal-status Critical Current

Links

Landscapes

  • Digital Magnetic Recording (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)

Abstract

PURPOSE: To enable to perform data reproduction with high accuracy by following the level variance, by operating the gate circuit based on the detected output of the synchronizing separation circuit to detect the maximum and minimum values of the signal and enabling level decision of reproducing signal based on this.
CONSTITUTION: The reproducing signal from the tape recorder recording the digital data signal with false television signal is input to the synchronizing separation circuit 13, and the gate switching control at the gate circuit 12 is made with the detected output, and only PCM signal is fed to the maximum voltage detection circuit 15 and the minimum voltage detection circuit 16 as the data signal to respectively detect the peak values of input signal. The level difference at the detectors 15, 16 is output to the comparator 11 as the comparison reference signal and the data identification is made for the reproducing signal from the video tape recorder for data reproduction.
COPYRIGHT: (C)1981,JPO&Japio
JP11004879A 1979-08-29 1979-08-29 Data separation circuit Pending JPS5634114A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11004879A JPS5634114A (en) 1979-08-29 1979-08-29 Data separation circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11004879A JPS5634114A (en) 1979-08-29 1979-08-29 Data separation circuit

Publications (1)

Publication Number Publication Date
JPS5634114A true JPS5634114A (en) 1981-04-06

Family

ID=14525776

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11004879A Pending JPS5634114A (en) 1979-08-29 1979-08-29 Data separation circuit

Country Status (1)

Country Link
JP (1) JPS5634114A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6145470A (en) * 1984-08-09 1986-03-05 Olympus Optical Co Ltd Reproducing device of slice level compensating signal

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6145470A (en) * 1984-08-09 1986-03-05 Olympus Optical Co Ltd Reproducing device of slice level compensating signal

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