JPS5651066A - Digital recording and playback device - Google Patents

Digital recording and playback device

Info

Publication number
JPS5651066A
JPS5651066A JP12776879A JP12776879A JPS5651066A JP S5651066 A JPS5651066 A JP S5651066A JP 12776879 A JP12776879 A JP 12776879A JP 12776879 A JP12776879 A JP 12776879A JP S5651066 A JPS5651066 A JP S5651066A
Authority
JP
Japan
Prior art keywords
circuit
clock signal
data
signal
reproduced
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12776879A
Other languages
Japanese (ja)
Inventor
Hideo Taki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP12776879A priority Critical patent/JPS5651066A/en
Publication of JPS5651066A publication Critical patent/JPS5651066A/en
Pending legal-status Critical Current

Links

Landscapes

  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Management Or Editing Of Information On Record Carriers (AREA)

Abstract

PURPOSE: To make easy the circuit constitution and its circuit control required for data processing, by recording another digital signal on another track, based on a clock signal picked up from a digital data on a recorded track.
CONSTITUTION: A reference clock generating circuit 3 outputs a clock signal S1 of predetermined frequency to a clock switching circuit 4. In this switching circuit 4, based on the reference signal in a playback data detection circuit 5, a clock signal is fed to a recording circuit 2. On the other hand, at the playback data detection circuit 5, for example, by detecting the frame synchronizing signal in playback data, whether or not the data is reproduced is discriminated, and if no data is reproduced in the switching circuit 4, the 1st clock signal S1 is fed to the recording circuit 2 and if reproduced, the 2nd clock signal S2 is fed to the circuit 2. Thus, the circuit constitution and the circuit control required for playback data processing can remarkably be simplified.
COPYRIGHT: (C)1981,JPO&Japio
JP12776879A 1979-10-02 1979-10-02 Digital recording and playback device Pending JPS5651066A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12776879A JPS5651066A (en) 1979-10-02 1979-10-02 Digital recording and playback device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12776879A JPS5651066A (en) 1979-10-02 1979-10-02 Digital recording and playback device

Publications (1)

Publication Number Publication Date
JPS5651066A true JPS5651066A (en) 1981-05-08

Family

ID=14968207

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12776879A Pending JPS5651066A (en) 1979-10-02 1979-10-02 Digital recording and playback device

Country Status (1)

Country Link
JP (1) JPS5651066A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0783715B1 (en) * 1981-11-23 1995-09-13

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0783715B1 (en) * 1981-11-23 1995-09-13

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