JPS5633765A - Absolute value circuit - Google Patents
Absolute value circuitInfo
- Publication number
- JPS5633765A JPS5633765A JP10949279A JP10949279A JPS5633765A JP S5633765 A JPS5633765 A JP S5633765A JP 10949279 A JP10949279 A JP 10949279A JP 10949279 A JP10949279 A JP 10949279A JP S5633765 A JPS5633765 A JP S5633765A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- terminal
- terminals
- comparator
- positive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
PURPOSE:To obtain the signal regarding the absolute value and the polarity of the high-accuracy input signal through a simple constitution of the circuit, by providing the switch element, the voltage comparator and the like. CONSTITUTION:The switch element 9 possesses two terminals 90 and 91 to be controlled plus the control terminal 92. And with application of the positive voltage to the terminal 92, a short circuit is secured between the terminals 90 and 91. And when the voltage of the terminal 92 becomes zero, an open state is secured between the terminals 90 and 91. In the voltage comparator 7, the output terminal 72 has the positive voltage when the voltage applied to the adverse- phase input terminal 70 is lower than that of the same-phase input terminal 71; While the voltage of the terminal 72 becomes zero vice versa. For instance, if the voltage ei at the point A and obtained from the input signal source 1 is positive, the voltage of the terminal 72 in the comparator 7 becomes zero. And thus the element 9 becomes open. Accordingly, the voltage of the same-phase and adverse-phase input terminals 21 and 20 become equal to the voltage ei under ei (>=0) defined for the voltage at the point A. And as a result, the voltage eo obtained at the output terminal 23 becomes equal to the voltage ei. And then eo=-ei is obtained under ii<0, and this shows that a conversion of eo=¦ei¦ has been given.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10949279A JPS5633765A (en) | 1979-08-27 | 1979-08-27 | Absolute value circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10949279A JPS5633765A (en) | 1979-08-27 | 1979-08-27 | Absolute value circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5633765A true JPS5633765A (en) | 1981-04-04 |
Family
ID=14511611
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10949279A Pending JPS5633765A (en) | 1979-08-27 | 1979-08-27 | Absolute value circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5633765A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58101561A (en) * | 1981-12-11 | 1983-06-16 | Kyocera Corp | Picture forming device |
-
1979
- 1979-08-27 JP JP10949279A patent/JPS5633765A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS58101561A (en) * | 1981-12-11 | 1983-06-16 | Kyocera Corp | Picture forming device |
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