JPS5631135A - Shift key lock display system - Google Patents

Shift key lock display system

Info

Publication number
JPS5631135A
JPS5631135A JP10660179A JP10660179A JPS5631135A JP S5631135 A JPS5631135 A JP S5631135A JP 10660179 A JP10660179 A JP 10660179A JP 10660179 A JP10660179 A JP 10660179A JP S5631135 A JPS5631135 A JP S5631135A
Authority
JP
Japan
Prior art keywords
shift key
gate
output
supplied
frequency
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10660179A
Other languages
Japanese (ja)
Inventor
Harumi Nakano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP10660179A priority Critical patent/JPS5631135A/en
Publication of JPS5631135A publication Critical patent/JPS5631135A/en
Pending legal-status Critical Current

Links

Landscapes

  • Input From Keyboards Or The Like (AREA)
  • Digital Computer Display Output (AREA)

Abstract

PURPOSE: To ensure a visual confirmation for both the states of the lock and the cancel of the lock of the shift key SK, by displaying the on/off state of the SK on the CRT screen through the blinking state having the different cursors.
CONSTITUTION: The shift key SK is a self-reset type switch, and the pulse signal is delivered from the one-shot circuit 14 for the fixed time and with every operation of the SK. Then the reversing action is given every time the pulse signal is supplied to the reversing circuit 15 to give an inversion between the output signal levels from the terminals Q and Q'. Then if the output levels of Q and Q' turn to 1 and 0 each by the operation of the SK, only the H counter performs counting. Then the count output synchronized with the frequency f1 is delivered to be supplied to the AND gate 13. On the other hand, the cursor blinking with the frequency f1 is displayed on the CRT by the output of the gate 13 when the cursor position signal sent from the coincidence circuit 12 and the timing signal T from the n-notation counter 2 are supplied to the gate 13. And the lock mode of the SK is confirmed. Then the K counter 17 starts when the SK is turned off. And the cursor is blinked with the frequency f2 to indicate the nonlock mode of the SK.
COPYRIGHT: (C)1981,JPO&Japio
JP10660179A 1979-08-23 1979-08-23 Shift key lock display system Pending JPS5631135A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10660179A JPS5631135A (en) 1979-08-23 1979-08-23 Shift key lock display system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10660179A JPS5631135A (en) 1979-08-23 1979-08-23 Shift key lock display system

Publications (1)

Publication Number Publication Date
JPS5631135A true JPS5631135A (en) 1981-03-28

Family

ID=14437646

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10660179A Pending JPS5631135A (en) 1979-08-23 1979-08-23 Shift key lock display system

Country Status (1)

Country Link
JP (1) JPS5631135A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5945647U (en) * 1982-09-17 1984-03-26 日本電気株式会社 CRT terminal device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5945647U (en) * 1982-09-17 1984-03-26 日本電気株式会社 CRT terminal device

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