US3605016A

US3605016A - Interval timer apparatus

Info

Publication number: US3605016A
Application number: US3713A
Authority: US
Inventors: Dana W Zimmerli; Duane F Rost
Original assignee: University of Iowa Research Foundation UIRF
Current assignee: University of Iowa Research Foundation UIRF; Iowa State University Research Foundation ISURF
Priority date: 1970-01-19
Filing date: 1970-01-19
Publication date: 1971-09-14
Anticipated expiration: 1988-09-14

Abstract

This invention relates to an interval timer apparatus for automatically timing a predetermined number of laps of known distance by a moving object, such as a race car, after the car has completed a predetermined number of practice laps; with the time or count of the timed laps being directly read out by a visual counter, and which count remains visible until a new count begins. The apparatus comprises a detection unit for producing a pulse for each interrupt by the car, which pulses are sent to a pair of preset shift register, one for the nontimed interrupts and one for the timed interrupts, with a standard clock frequency gated to a decade counter and display unit when the pulses have been shifted to the timed interrupt register.

Description

United States Patent [72] Inventors Dana W. Zimmerli; 3,508,034 4/1970 Toyana et al. 235/92 [2 1 pp No both low. Primary Examiner-Alfred E. Smith Filed J 1970 Attorney-Henderson & Strom [45] Patented Sept. 14,197] [73] Assignee Iowa State University Research Foundation, Inc. Ames, lovvn ABSTRACT: This invention relates to an interval timer ap- {541 INTERVAL TIMER APPARATUS paratus for automatically timing a predetermined number of 9 Chill, 3 Dn'in its laps of known distance by a moving ob ect, such as a race car,

after the car has completed a predetermined number of prac- [52] US. Cl. 324/186, fl with the i or count f the timed laps being 324/178 directly read out by a visual counter, and which count remains [5|] Int. 604(9/00 visible umj] a new count begins The apparatus comprises a [50] Field 324/186, detection unit f producing a pulse f each interrupt by the 179i 235/92 92 TA car, which pulses are sent to a pair of preset shift register, one R t cm for the nontimed interrupts and one for the timed interrupts, [56] e with a standard clock frequency gated to a decade counter UNITED STATES PATENTS and display unit when the pulses have been shifted to the 2,6l2,948 10/1952 Malottet al. 324/l78X timed interrupt register.

2 In 'ferrupflnverrupf' 5 De/ncfar 5/7dpar 6m; fi-e-mnf Pay/3ft)- daum fivflwpfilginkr a l i Sal/mg Jail/0g Sui/:6 1min Ju /7'56 \../Z 4 Chub-0 Cbumar Pesef Caunfer and INTERVAL TIMER APPARATUS BACKGROUND OF THE INVENTION This invention relates to a timer for use in connection with motor vehicle racing wherein the time of a single vehicle about a closed course or track of known distance is matched and compared to the time of one or more other vehicles about the same track.

Usually, this type of racing, which is of the beat the clock" type competition, involves each contestant making several practice or nontimed laps prior to their completing a predetermined number of timed laps.

Various mechanisms from stop watches to more sophisticated timing equipment is available for recording the amount of lapsed time the single vehicle or car took to complete the course. Certain of these and others adaptable for the same use are disclosed in U.S. Pats. Nos. 2,612,948; 2,787,738; 3,037,166; 3,133,189; 3,171,953; 3,218,553; and 3,325,729. A great disadvantage of the present day interval timer is its dependence upon the human element, that is, the operator of the timer. He must still make too many decisions with particular respect to when to start the timer, and/or when to stop it. Still another disadvantage of present day timers is their inability to provide a direct read out of the racing time, and to maintain that read out visible at all times until the beginning of the next timing.

The present interval timer is designed to overcome these and other disadvantages of present day timers.

SUMMARY OF THE INVENTION This invention relates to an interval timer comprising a pulse generator responsive to movement of a physical object, such as a car, past the generator, with each pulse fed first to a preset register of nontimed pulse intervals, which pulses are then gated to another preset register which counts the preset number of time pulses and then effects a cessation of the apparatus. When the apparatus was activated, a standard clock frequency was produced by a crystal oscillator and directed to a closed gate, the latter being opened in response to completion of the count by the first register, whereby the clock frequency is then directed to a standard counter, with the count displayed in decimal values of minutes and seconds. An automatic reset circuit is provided for the counter and display unit, which circuit is operable only in response to completion of the nontimed pulse count so that the complete timed count is visually maintained at all times.

An object of this invention is to provide a new and novel interval timer.

Another object of this invention is to provide an interval timer which provides a direct read out of only the intervals desired to be timed, and which intervals may begin after any predetermined number of intervals have been detected and may end again after any additional predetermined number of intervals have been detected.

Still another object of this invention is to provide an interval timer wherein the number of practice laps and to-be-timed laps are automatically preset into the apparatus such that no operator decision is necessary to aid the timer count and display the time of the timed laps.

Another object of this invention is to provide an interval timer wherein at the end of the timing operation, the apparatus is completely reset to accept the next preset situation to be timed, but wherein the last count of the timer remains visibly displayed until the exact beginning of the next timed count.

It is still another object of this invention to provide an interval timer which is simple, economical and efiective.

These and other objects will become readily apparent upon reference to the following description and accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of the interval timer of the present invention;

FIG. 2 is a schematic diagram of the interval timer partly in block diagram and partly in circuit schematic form; and

FIG. 3 is a schematic diagram of a shift register part of the timer, partly in block diagram and partly in circuit schematic form.

DESCRIPTION OF THE PREFERRED EMBODIMENT In FIG. 1, the interval timer of the present invention is shown in block diagram form and comprises a source 1 of input pulses, each pulse being an interrupt caused by the vehicle being timed passing by the source. The interrupt pulses are sent through a means 2 to which the source 1 is connected for shaping the signal nature of the pulses or interrupts, and then the shaped interrupts are forwarded to a practice lap register 3, connected with the means 2, where they are counted.

After communication between the car driver and the timer operator, who may be one and the same, a predetermined number of practice laps by the car are determined to be made prior to the lap or laps to be timed, as well as there being determined a number of timed laps. The former number is preset by a setting switch 4 into the practice lap register 3 with which it is connected, and the latter number of timed laps is preset into a timed lap register 6 by another setting switch 12 connected therewith.

When the register 3 has received and counted the number of nontimed or practice laps set therein, it stops registering the pulses and emits a signal which is sent through a line 7 to a pulse control gate 5, which gate 5 had prevented the shaped interrupts being set to the register 3 from also being sent to the timed lap register 6. The signal, however, opens the gate 5 to permit the next interrupt pulse to be received by the register 6 to which the gate 5 is connected.

The signal sent through line 7 from the practice lap register 3 is also sent to a normally closed timing control gate 8 which is connected also to the register 6. The gate 8 is used to control the transmission of signals from a timing unit 9 which emits a standard clock frequency and sends the frequency to the gate 8 with which it is connected and also to a counter reset 11 with which it is connected. The timing control gate 8 is connected not only to the counter reset 11 but also to a decade counter and display unit 10.

The unit 10 displays the count of the last timed lap or laps, but is reset to a predetermined base, zero for example, by action of the counter reset 11 receiving a signal from the gate 8 in response to the latter receiving the signal from the practice lap register that the number of practice laps had been completed. Simultaneously with the reset action of the counter unit 10, the clock frequency is fed through the timing control gate 8, open in response to receiving the first signal from the practice lap register 3, to the counter unit 10, wherein the count continues and is displayed until the count of the timed laps set into the register 6 is completed, whereby a signal therefrom closes the timing control gate 8, preventing further transmission of the clock frequency, and effects a reset of the entire apparatus such that it can begin another cycle.

More specifically, referring to FIGS. 2 and 3, the source I of input pulses may comprise any suitable source for detecting the passage of the car (not shown), such as a mechanical switch, or a photoelectric device such as a phototransistor 101. The signal or wave-shaping means 2 comprises a quartet of integrated circuit inverters 103, a monostable multivibrator 104, and another trio of inverters 105. The inverters I03 shape the interrupt signals into a square waveform for input into the multivibrator 104, and the inverters also invert and amplify the said signals for input into the shift registers I07 and 106. The inverters 103 and 105 may comprise, for example, any known form of circuitry for performing their prescribed functions.

The monostable multivibrator 104 is a device to inactivate the input from the interrupt source 101 for a predetermined period of time, for example, a few seconds, after each interrupt. Thus, should the car have a bumper or any other leading object which might cause a quick pair of interrupts, the second one of which would be false, the multivibrator would ignore the false, later interrupt. The multivibrator 104 may comprise any of the types of circuits making up some known in the art for performing this prescribed function.

The practice lap register 3 and the timed lap register 6 of P10. 1 are shown as 107 and 106, respectively, in FIG. 2, being connected by lines 1070 and 106a to the inverter group 105. Their respective setting switches are indicated at 127 and 126. As these shift registers are identical, an embodiment of one form thereof is set out in more detail in FIG. 3. Input lines 107a and/or 106a are shown at A leading to four flip-flop,

bistable devices

201, 202, 203 and 204, and the setting switch 205, either 127 or 126 in FIG. 2, is connected as illustrated in FIG. 3 with the four flip-flops to determine the starting, and the ending, of the shift register. Input line E is used to reset the register to zero, and B, C and D are the output lines required. The bistable devices may, for example, be of any known type for the flip-flop purpose required.

Referring back to FIG. 2, it is seen that outputs B and C from practice lap register 107 are connected to a NOR gate 108, which fulfills the function of the pulse or interrupt control gate 5 of FIG. 1, with the input from gate 108 clearing the timed laps register 106 when the count of register 107 is complete. Output D from register 107 is also connected to the three input NOR gates 109 and 110, and the bistable flip-flop l14b. Outputs D and C from the timed lap register 106 are connected also to the NOR gates 109 and 110. Gate 109 clears register 107 when the interrupt count is complete, and gate 110 is a part of the timing control gate 8 of FIG. 1, opening up the counter and display unit 113 to the oscillator 111 when the count of the register 107 is complete.

The NOR gates 109 and 110 may, for example, be of any known type for their purpose, and the counter and display unit 113 may comprise, for example, as suitable decade counter. The oscillator may be, for example, a 100 kilohertz crystal oscillator for producing a standard clock frequency. Of note, a divide-by-IOO counter 112 is connected between the NOR gate 110 and the counter 113 for scaling down the crystal oscillator signal from, for example, 10" seconds to 10 seconds or 0.001 seconds, for example. The counter 112 may, for example, be of the types of known counters for this purpose. The counter and display unit 113 may comprise, for example, a group of basic decade counters of integrated circuits. The counter 113 may have sufficient tags to decode and provide a read out of the time count in terms of minutes, second, and tenths, hundreths and thousandths of seconds.

The counter reset 11 of HG. 1 is illustrated more specifically by a pair of flip-flop bistable devices 114a and [14b connected as illustrated with a gate 115 for resetting the counter and display unit 113, to zero for example, when the practice lap register 107 has completed its count. These devices and the gate may also be of conventional circuitry for their intended purpose.

A pushbutton 116, a gate 117, and a trio of diodes 118a, 1181) and 1180 electrically connected as illustrated in FIG. 2, allow the operator to reset the entire interval timer apparatus, except the counter unit 113, in case of an abnormal completion.

For a typical operation of the interval timer apparatus, the phototransistor device 101 is set up its light beam across a race track of the closed course type and of a known distance. The drivers of a number of competing cars determine that each car will make two practice laps and three timed laps about the track. Each time the car on the course breaks the beam of the detector device 101, a pulse is generated, termed hereinafter an interrupt, as the beam is interrupted.

The operator of the timer apparatus sets the number two for the practice laps into the register 107, by manipulating the setting switch 127, and sets in the number three for the laps to be timed into the register 106, by manipulating the setting switch 106. The apparatus derives voltage from a conventional l2-volt storage battery, for example, and has a master control switch, which when on, supplies power to the circuitry of the apparatus. With power new supplied, the crystal oscillator 111 transmits its frequency through line 111a (FIG. 2) to the gate 110, closed at the time such that the counters 112 and 113 are not counting.

One of the cars makes its two practice laps, the interrupts each passing through the wave shaping and amplifying inverters 103 and 105, as well as the disarming device 104 for providing consistency to the apparatus, and is received and counted by the register 107 emits a signal to the gates Upon completion of the count of two for the two practice laps, the register 107 emits a signal to the

gates

108, 109, 110 and flipflop 114b. At gate 108, it is thereby opened such that the register 106 is cleared to accept the interrupts for the timed laps through line 106a.

The signal at flip-flop 114b effects a reset of the counter and display unit 113 from its last timed count to a base, zero for example.

The signal at gate 110 opens same and permits the signal from the oscillator 11 l, at 10 seconds, to be passed to the divide-by-IOO counter 112 where the signals are scaled down to 10 seconds before being fed to the counter and display unit. Thus, in response to the completion of the nontimed count, the timed lap register 106 begins counting the next three interrupts, and the counter 113, reset to zero by the reset unit 114a, l14b and 115, receives and displays the standard clock frequency from the oscillator 111.

When the register 106 counts the third interrupt, indicative of the end of the three timed laps, it emits a signal on line 1061: which is fed to the timing control gate 110, whereby the gate is closed and no further signals from the oscillator are transmitted to the counter 113. The count of the counter 113 is thus stopped, such that it displays the clock total for the three laps. A signal from the register 106 is also fed out on line 106d to gate 109, whereby the register 107 is cleared to be automatically ready for the next sequence of nontimed and timed laps of the next car.

We claim:

1. An interval timer apparatus comprising:

means for producing a number of interrupts;

means for presetting a number of nontimed interrupts;

first means for counting said nontimed interrupts and responsive to the completion of said nontimed interrupts to emit a first signal;

means for presetting a number of timed interrupts;

second means for counting said timed interrupts and responsive to the completion of said timed interrupts to emit a second signal;

a first gate responsive to said first signal for gating said interrupts to said second counting means;

means for supplying a standard clock frequency;

third means for counting the clock frequency;

a second gate for gating the clock frequency to said third counting means, said second gate responsive to said first signal to transmit the clock frequency, and responsive to said second signal to stop transmission of the clock frequency;

reset means operable in response to the clock frequency and to said first signal to reset said third counting means; and means for displaying the count off the third counting means.

2. An interval timer apparatus as defined in claim 1, wherein said interrupts producing means includes a light source, and a photoelectric cell for receiving a light beam from said source.

3. An interval timer apparatus as defined in claim 2, wherein each said first means and second means includes a plurality of bistable devices connected to receive and store said interrupts; and for producing a signal upon completion of wherein said clock frequency displaying means displays the clock total until reset by said reset means to a predetermined base for counting purposes.

8. An interval timer apparatus as defined in claim 1, and wherein said reset means is operable only in response to receiving said first signal.

9. An interval timer apparatus as defined in claim 1, and wherein means is provided for disarming said interrupts producing means for a predetermined period of time following each interrupt.

Claims

1. An interval timer apparatus comprising: means for producing a number of interrupts; means for presetting a number of nontimed interrupts; first means for counting said Nontimed interrupts and responsive to the completion of said nontimed interrupts to emit a first signal; means for presetting a number of timed interrupts; second means for counting said timed interrupts and responsive to the completion of said timed interrupts to emit a second signal; a first gate responsive to said first signal for gating said interrupts to said second counting means; means for supplying a standard clock frequency; third means for counting the clock frequency; a second gate for gating the clock frequency to said third counting means, said second gate responsive to said first signal to transmit the clock frequency, and responsive to said second signal to stop transmission of the clock frequency; reset means operable in response to the clock frequency and to said first signal to reset said third counting means; and means for displaying the count off the third counting means.

3. An interval timer apparatus as defined in claim 2, wherein each said first means and second means includes a plurality of bistable devices connected to receive and store said interrupts; and for producing a signal upon completion of said storing when a predetermined number of interrupts preset into said bistable devices has been stored.

4. An interval timer apparatus as defined in claim 3, wherein said standard clock frequency supplying means includes a crystal-controlled oscillator.

5. An interval timer apparatus as defined in claim 4, wherein said third means includes a decade counter.

6. An interval timer apparatus as defined in claim 4, wherein said reset means includes a pair of bistable devices and a NOR gate interconnected therewith.

7. An interval timer apparatus as defined in claim 1, wherein said clock frequency displaying means displays the clock total until reset by said reset means to a predetermined base for counting purposes.