GB1283809A - Improvements in or relating to the automatic measurement of pulse repetition intervals - Google Patents

Abstract

1283809 Measurement of pulse repetition intervals MULLARD Ltd 8 Dec 1970 58256/70 Heading G4H A method of and apparatus for the automatic measurement of pulse repetition intervals (P.R.I.'s) comprises the measurement of the intervals between the first and second and second and third pulses of three consecutive pulses in a track of at least three pulses and comparing the measurements, wherein if the difference lies within a given amount, then one of the intervals is taken as the measured amount, whereas if it does not, after one or more repeated measurements of succeeding intervals, then the amount or tolerance is widened. As shown, an input pulse track is applied at IP and adapted at PS to provide pulses of fixed and known duration separated by intervals to be measured, the signal being inverted at I1 to allow clock pulses from CP to pass to counter CTR. The uninverted signal is taken to a series of monostables M1-M4, M1 adapted to be triggered by an incoming standardized pulse and to trigger M2 on returning to its stable condition, M2 then triggering M3 &c. Upon the triggering of monostable M3, a signal is applied to a store ST via gate A3 to cause the contents of counter CTR to be transferred into the store ST, the counter being reset by M4 prior to the appearance of the next interval. The contents of counter CTR and store ST are then compared by subtraction at SUB and a binary number representing the difference, transferred to MC, wherein a binary "1" or "0" output is provided according as to whether the difference is within or outside a close tolerance defined at CTS. A "1" output causes a second counter CC to increment by 1 on its "UP" side, and a "0", increment on its "DOWN" side upon receiving of a clocking pulse from M2 in the subsequent standard pulse period, a "1" output at MC also being gated at A4 to trigger monostable M5 having a duration of about 2 seconds to apply an inhibit signal at A3 in order that subsequent intervals will be compared at SUB with the contents of the store at the beginning of the M5 period which contents are displayed at ID via gate A2. In the event of an aggregate 8 counts on the "UP" side of counter CC, gate HCG is enabled to trigger monostable M6, having a duration of several seconds, to also apply an inhibit and display signal at A3, A2 respectively, and illuminate lamp HC1 to indicate the reading at ID is of "high confidence". In the event of an aggregate 8 appearing on the "down" side of CC, gate LCG is enabled to trigger monostable M7 to illuminate a lamp WTD and apply a signal of several seconds duration to WTS whereby the tolerance level at MC is widened for this duration, the rest of the circuit functioning subsequently as described above. The tolerance levels at MC may be made proportional to the count in the counter CTR and the members CTS, WTS, MC comprise NAND- and exclusive OR- gate logic circuitry, Fig. 2 (not shown).