JPS5629759A - Byte mark register control system for memory device - Google Patents
Byte mark register control system for memory deviceInfo
- Publication number
- JPS5629759A JPS5629759A JP10461479A JP10461479A JPS5629759A JP S5629759 A JPS5629759 A JP S5629759A JP 10461479 A JP10461479 A JP 10461479A JP 10461479 A JP10461479 A JP 10461479A JP S5629759 A JPS5629759 A JP S5629759A
- Authority
- JP
- Japan
- Prior art keywords
- byte mark
- transfer
- pattern
- register
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
PURPOSE: To eliminate both the production and transfer of the byte mark prior to the transfer of the writing data by setting the fixed byte mark pattern to the byte mark register after completion of the instruction fetching, thus ensuring a high-speed memory access.
CONSTITUTION: It is supposed that the instruction fetching completes with the signal IEND turned to 1. And thus "1111" of the fixed byte mark generating circuit 8 is delivered from the OR circuit 10. And if the signals SBMU, SMBFL and SMBL are off and the signal ADR29 is "1" each, the pattern "1111" is set to the byte mark register 7-1. And in case the signal *ADR29 is "1", the pattern "1111" is set also to the register 7-0. In such way, the fixed byte mark pattern "1111" is set to the registers 7-0 and 7-1 each after completion of the instruction fetching. Thus the production and transfer of the byte mark prior to the transfer of the writing data can be eliminated. As a result, the memory access is possible in a high speed.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10461479A JPS5629759A (en) | 1979-08-17 | 1979-08-17 | Byte mark register control system for memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10461479A JPS5629759A (en) | 1979-08-17 | 1979-08-17 | Byte mark register control system for memory device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5629759A true JPS5629759A (en) | 1981-03-25 |
Family
ID=14385309
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10461479A Pending JPS5629759A (en) | 1979-08-17 | 1979-08-17 | Byte mark register control system for memory device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5629759A (en) |
-
1979
- 1979-08-17 JP JP10461479A patent/JPS5629759A/en active Pending
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