JPS5627454A - Information processor - Google Patents

Abstract

PURPOSE: To perform address arithmetic processing at a high-speed by providing a memory unit in which each register is available for two words of X bytes and Y bits and an arithmetic unit that can process data of this number of bits at a time.

CONSTITUTION: Local storage LS22 includes Y(Y=4)-bit bank BK₁ and X(X=2)- byte band BK₂ to compose one word of 20 bits. Then, LS22 has 4-byte registers and each register consists of the high-order and low-order two bytes and four bits respectively. Arithmetic unit 21 has 20 bits for both right and left input data widths and the input data are supplied through input registers 25 and 26 and used for both address arithmetic and operand arithmetic. The output of arithmetic unit 21 is divided by four buses 24 into four, eight, four, and four bits, which are set in LS or address register 27. When the result of the operand arithmetic is written in register GRA of LS, the low-order four bits of the high-order word are written at the high-order four bits of the low-order word through the selection of selector circuit 29.

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