JPS5624624A - Logic tracer - Google Patents

Logic tracer

Info

Publication number
JPS5624624A
JPS5624624A JP10004579A JP10004579A JPS5624624A JP S5624624 A JPS5624624 A JP S5624624A JP 10004579 A JP10004579 A JP 10004579A JP 10004579 A JP10004579 A JP 10004579A JP S5624624 A JPS5624624 A JP S5624624A
Authority
JP
Japan
Prior art keywords
data
memory
clock
measured
sample data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10004579A
Other languages
Japanese (ja)
Inventor
Seiichi Sugaya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10004579A priority Critical patent/JPS5624624A/en
Publication of JPS5624624A publication Critical patent/JPS5624624A/en
Pending legal-status Critical Current

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  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To automatically control the start and completion of trace by corresponding the sample data of the data to be measured to the time series to have such a construction as to extract the generation of a predetermined condition.
CONSTITUTION: After the trigger TR is given, the trace data memory 1 in which the data DT to be measured is recorded in time series and synchronously with the clock CL, the sample data line memory 2 in which the smaple data is stored in time series, and a comparison circuit 3 are disposed. The test object data processing device carries out the processing and the data DT becomes the data A, then the comparison circuit 11 produces a coincidence output to set FF13 and at this time, the memory 2 outputs the data A as the sample data and thereafter synchronizes with the clock CL to output the sample data P, Q, R... following the data A successively. Then, at a certain time point, when the data to be measured does not coincide with the sample data, the circuit 3 at this point forms the trigger TR as a logic "1" and thereafter, the memory 1 synchronizes with the clock CL to record the data DT successively.
COPYRIGHT: (C)1981,JPO&Japio
JP10004579A 1979-08-06 1979-08-06 Logic tracer Pending JPS5624624A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10004579A JPS5624624A (en) 1979-08-06 1979-08-06 Logic tracer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10004579A JPS5624624A (en) 1979-08-06 1979-08-06 Logic tracer

Publications (1)

Publication Number Publication Date
JPS5624624A true JPS5624624A (en) 1981-03-09

Family

ID=14263528

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10004579A Pending JPS5624624A (en) 1979-08-06 1979-08-06 Logic tracer

Country Status (1)

Country Link
JP (1) JPS5624624A (en)

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