JPS5617548A - Signal storing device - Google Patents
Signal storing deviceInfo
- Publication number
- JPS5617548A JPS5617548A JP9213379A JP9213379A JPS5617548A JP S5617548 A JPS5617548 A JP S5617548A JP 9213379 A JP9213379 A JP 9213379A JP 9213379 A JP9213379 A JP 9213379A JP S5617548 A JPS5617548 A JP S5617548A
- Authority
- JP
- Japan
- Prior art keywords
- control
- signal
- signals
- transmission
- fault
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Maintenance And Management Of Digital Transmission (AREA)
- Storing Facsimile Image Data (AREA)
Abstract
PURPOSE:To exclude the fault occurrence detecting circuit and thus reduce the whole hard scale, by monitoring the presence or absence of the logic conflicet and the timing fault by the control circuit of each part for the transmission/reception state of the control signals which are transferred among the parts. CONSTITUTION:An integrated control is given to control units 12', 13', 14' and others through central processor 11. Then the signal conversion is carried out when the signals are transmitted and received to/from the terminal by signal reception and transmission converting parts 12 and 13 which receive the control of control circuits 12' and 13' respectively. The signals converted into the digital signals are stored at storing part 15. Furthermore, the signal transmission/reception is carried out to other signal storing devices by interdevice signal transfer part 14 which receives the control of control circuit 14'. Then a monitor is given control circuits 12', 13' and 14' to the presence or absence of the logic conflict and the timing fault for the transmission/reception state of the control signals which are transferred among those parts. Then the detection result is displayed at fault display part 16 via processor 11.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54092133A JPS5852380B2 (en) | 1979-07-21 | 1979-07-21 | signal storage device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP54092133A JPS5852380B2 (en) | 1979-07-21 | 1979-07-21 | signal storage device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5617548A true JPS5617548A (en) | 1981-02-19 |
JPS5852380B2 JPS5852380B2 (en) | 1983-11-22 |
Family
ID=14045928
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP54092133A Expired JPS5852380B2 (en) | 1979-07-21 | 1979-07-21 | signal storage device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5852380B2 (en) |
-
1979
- 1979-07-21 JP JP54092133A patent/JPS5852380B2/en not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS5852380B2 (en) | 1983-11-22 |
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