JPS56161725A - Logical package - Google Patents

Logical package

Info

Publication number
JPS56161725A
JPS56161725A JP6445780A JP6445780A JPS56161725A JP S56161725 A JPS56161725 A JP S56161725A JP 6445780 A JP6445780 A JP 6445780A JP 6445780 A JP6445780 A JP 6445780A JP S56161725 A JPS56161725 A JP S56161725A
Authority
JP
Japan
Prior art keywords
logical
signal
multivalue
binary
main circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6445780A
Other languages
Japanese (ja)
Inventor
Akihiko Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP6445780A priority Critical patent/JPS56161725A/en
Publication of JPS56161725A publication Critical patent/JPS56161725A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/082Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using bipolar transistors
    • H03K19/0823Multistate logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To mitigate the limit as to the storing capacity of logical circuit and to make easy the connection between logical packages, by using a multivalue logical signal for the input and output of logical packages and decreasing the number of input and output terminals required. CONSTITUTION:A main circuit 1 consists of binary logical circuits. An external input signal is given to an input terminal group 2 in the form of multivalue logical signal and given to the main circuit 1 after being converted into a binary logic signal at a conversion circuit 4. The binary logical operation is made at the main circuit 1, the binary logical output signal of the main circuit 1 is converted into a multivalue logic signal at a conversion circuit 5 and transferred to the external devices as the multivalue logical signal from an output terminal group 3.
JP6445780A 1980-05-15 1980-05-15 Logical package Pending JPS56161725A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6445780A JPS56161725A (en) 1980-05-15 1980-05-15 Logical package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6445780A JPS56161725A (en) 1980-05-15 1980-05-15 Logical package

Publications (1)

Publication Number Publication Date
JPS56161725A true JPS56161725A (en) 1981-12-12

Family

ID=13258782

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6445780A Pending JPS56161725A (en) 1980-05-15 1980-05-15 Logical package

Country Status (1)

Country Link
JP (1) JPS56161725A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0074722A2 (en) * 1981-08-17 1983-03-23 Development Finance Corporation Of New Zealand Multilevel logic circuit
EP0179310A2 (en) * 1984-10-26 1986-04-30 International Business Machines Corporation Trinary interface for binary logic

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0074722A2 (en) * 1981-08-17 1983-03-23 Development Finance Corporation Of New Zealand Multilevel logic circuit
EP0179310A2 (en) * 1984-10-26 1986-04-30 International Business Machines Corporation Trinary interface for binary logic

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