JPS56158591A - Time switch for time division exchanger - Google Patents
Time switch for time division exchangerInfo
- Publication number
- JPS56158591A JPS56158591A JP6320880A JP6320880A JPS56158591A JP S56158591 A JPS56158591 A JP S56158591A JP 6320880 A JP6320880 A JP 6320880A JP 6320880 A JP6320880 A JP 6320880A JP S56158591 A JPS56158591 A JP S56158591A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- given
- spmo
- time
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
Abstract
PURPOSE:To obtain a time switch strongly resistive to failure over the broad range of a line region, by making the interface between the time switches simple, through constituting one stage of time switches with almost the same two time switches. CONSTITUTION:One stage time switch is constituted with almost the same two time switches, and the output of a channel memory SPMO is given to the input of a storage circuit LATCH0 via a selection circuit SEL01 according to the content of FFs 00,01 and 10,11, and the output of the memory SPMO is given to the input of a storage circuit LATCH1 via a selection circuit SEL11. Further, a selection circuit SEL03 selects the output of an addition circuit LDD01 and a selection circuit SEL13 selects the output of the addition circuit 10. Further, at the 1st cycle, a highway HWOT is given according to the selection signal, and the data from a channel storage memory HMO is given to the input address of the memory SPMO; and at the 2nd cycle, the data from the memory HMO is given to the address of the memory SPMO with N/2.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6320880A JPS56158591A (en) | 1980-05-13 | 1980-05-13 | Time switch for time division exchanger |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP6320880A JPS56158591A (en) | 1980-05-13 | 1980-05-13 | Time switch for time division exchanger |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56158591A true JPS56158591A (en) | 1981-12-07 |
Family
ID=13222545
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP6320880A Pending JPS56158591A (en) | 1980-05-13 | 1980-05-13 | Time switch for time division exchanger |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56158591A (en) |
-
1980
- 1980-05-13 JP JP6320880A patent/JPS56158591A/en active Pending
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