JPS56157162A - Inter-office monitor signal bit holding system - Google Patents

Abstract

PURPOSE:To fix the circuit state to the condition before occurrence of a fault even when a step-out is detected and thus prevent the occurrence of a misconnection, etc., by adding a multiframe step-out detecting circuit and an inter-office monitor signal bit holding circuit to the outgoing highway of a time-division switchboard. CONSTITUTION:Both an intra-office monitor signal bit (S bit) and the S bit sent from a multiframe signal sending device are supplied to a multiplex circuit 107 via a reception buffer circuit 105 and a buffer memory circuit 106. At the same time, the signal supplied from the reception side 102 of a frame aligner that performs an interface matching with a transmitting device is also supplied to the circuit 107 in the same way. These signal bits and signal are sent to an S-bit receiving device 101 and a frame aligner 103 via a time-division switch 108 and a multiplexer 109. In the case of a multiframe step-out, this step-out is detected through a detecting circuit 140. A change-over circuit within an S-bit holding circuit 120 is switched, and a multiframe preceding S bit held at the circuit 120 is inserted into a signal time slot of the highway to be sent to another office and thus to secure a state before occurrence of a fault.