JPH0436498B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an autonomous testing system for an inter-office supervisory signal transmitting circuit and an inter-office supervisory signal receiving circuit in a digital signaling device of a period-divided exchange.

A multi-frame synchronization test method for an inter-office supervisory signal transmitting circuit and an inter-office supervisory signal receiving circuit in a conventional time division switch will be described with reference to FIG. In FIG. 1, 100 is an inter-station supervisory signal transmission circuit (SSS);
101 is an inter-station monitoring signal receiving circuit (SSR), 102
1 is a time division communication path, 103 is a digital transmission path, 1
04 is a control device (CNT), and 105 is a digital signal device.

In the figure, inside the digital signal device 105,
The SSS 100 and SSR 101 multiplex process inter-office monitoring signals (hereinafter abbreviated as S bits) of lines for n HWs 103 accommodated in the time division communication path 102. First, the SSS 100 transmits the S bits of the line designated by the control device CNT 104 to a predetermined bit position that is time-division multiplexed in a multi-frame format, and the function of creating a multi-frame pattern. Send a bit.

On the other hand, the SSR 101 receives S bits multiplexed in a multiframe format from the time division channel 102, and performs multiframe synchronization.
The S bit is temporarily stored in the address corresponding to the line on the memory of CNT 104 in preparation for reading the S bit from CNT 104. Additionally, line abnormalities are detected by monitoring multi-frame patterns.

Devices multiplexed by time-division processing such as SSS100 and SSR101 are not shown in the figure, but they usually consist of a memory and a common logic section, and a failure in the memory or common logic section will affect all multiplexed lines. , the interference waves and range are large. Especially SSS100
A failure will cause opposing stations to malfunction all at once. Moreover, failure of the SSR 101 causes erroneous billing. Therefore, in order to detect failures early, memory failures are detected by parity checks.

On the other hand, the conventional common logic unit failure detection method uses a method of providing a test device. In other words, SSS fault detection is performed by the S bit receiving circuit in the test equipment.
By receiving the signals sent from SSS,
In addition, SSR fault detection can be performed by having the SSR receive a signal sent from the S-bit transmitting circuit in the test equipment, or by transmitting a signal from the SSS to the time-division channel by setting the time-division channel's bus. This is done using a signal return method using a time-division communication route by receiving the signal at the same time.

However, in such conventional test methods,
Because signals pass through other devices, it is necessary to distinguish between faults within the own device and faults in other devices.Also, when testing, inter-control communication between the control device of the other device and the control device of the own device is required. There is a frequency of testing that is necessary.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-frame synchronization test method that eliminates the drawbacks of the conventional test methods described above, simplifies testing of inter-office supervisory signal transmitting circuits and receiving circuits, and takes autonomous testing into consideration.

The present invention provides a path connecting an inter-office supervisory signal transmitting circuit and a receiving circuit, a signal transmitted from the transmitting circuit (SSS) based on frame phase conditions of an input signal and an output signal of a time-division channel, and a signal transmitted from the above-mentioned receiving circuit. By providing a means for absorbing the frame phase difference of the received signal in the circuit (SSR) and a means for setting and canceling the above-mentioned connection path, the multi-frame pattern sent from the SSS can be transferred to the SSR in the same digital signal equipment. This is to perform a multi-frame synchronization test of SSS and SSR by directly receiving the signal.

In other words, the multiframe pattern sent from the SSS can be constantly monitored by the multiframe synchronization circuit in the SSR by setting a connection path. Also
The SSR's multiframe synchronization circuit can be constantly monitored to ensure that it correctly receives the multiframe patterns sent from the SSS. Furthermore, by canceling the connection path, it is possible to cause a multi-frame pattern abnormality, and it is also possible to perform a pseudo-normal test of the SSR's multi-frame synchronization circuit.

Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 2 is a diagram showing one embodiment of the test method according to the present invention, and FIG. 3 is a time chart showing the circuit operation of FIG. 2. In FIG. 2, the same symbols as those in FIG.
It consists of a 00, 2-1 selector (SEL) 106 and an 8-bit shift register (SR) 107.
Further, 101' is an inter-station supervisory signal receiving section, which includes an inter-station supervisory signal receiving circuit (SSR) 101 and an AND gate 10.
8 and 2-1 selector (SEL) 109. Furthermore, 110 is a transmitting section 100' and a receiving section 1.
Connection paths that directly connect 01', a and c are respectively
SEL106, 109 select signal, b is a signal that controls gate 108 on/off, d is SSS1
00, e is a signal on the connection path 110, f is a signal sent from the time division communication path 102, and g is a signal input to the SSR 101. Further, in FIG. 3, the same symbols as those shown in FIG. 2 indicate corresponding signals, and A and B are signals indicating frame positions of SSS 100 and SSR 101, respectively. Note that the numbers in each time slot indicate the signal content of each time slot, and T indicates the signal content of the test time slot.

Next, the operation of the circuit shown in FIG. 2 will be explained using FIG. 3. First, the SSS 100 sends a signal d as shown in FIG.
Suppose that it is sent on 02. At this time, the select signal a is sent to the selector (SEL) 106 at the timing shown in FIG. 3 (when transmitting the test time slot T).
, the SEL 106 selects the transmission signal d of the SSS 100 and causes the shift register (SR) 107 to input the content T of the test time slot at this time. After that, select the output signal of SR107,
The 8-bit delayed output signal of SR107 is output to SR10.
7 is input. As a result, the signal content T of the test time slot is transmitted to all the time slots on the connection path 110 as shown in e in FIG. 3 by circulating through the SR 107 in units of 8 bits.

Next, in the inter-office monitoring signal receiving section 101', the signal f sent from the time-division communication path 102 according to the frame position B and the signal e sent via the gate 108 are sent to a selector (SEL) by a select signal C. )109 to select. That is, as shown in Fig. 3, when the select signal C is applied to the SEL 109 at the timing of receiving the test time slot, the SEL 109 selects the signal e, otherwise selects the signal f and outputs the signal g. do. As a result, the SSR 101 can input the signal content T at the position of the test time slot, and testing can be performed during normal service without affecting other time slots. Also SSS100, SSR10
Each frame phase difference of 1 can be absorbed.

Note that the gate 108 is connected to the connection path 1 by the signal b.
10 is provided for setting and canceling the settings. That is, by turning off the gate 108 with the signal b, the connection of the connection path 110 can be released, thereby stopping the multi-frame signal and performing a pseudo-normal test of the multi-frame synchronous rotation in the SSR 101. .

As described above, according to the present invention, an autonomous test of multi-frame synchronization can be performed within a digital signal device without going through other devices, and there is no need for troubleshooting or communication between control devices.

In addition, by using empty time slots that are not used for normal services as test time slots, we can
It becomes possible to test at all times.

Furthermore, the control device makes it possible to test the transmission functions of the inter-office supervisory signal transmission circuit and reception circuit using the line accommodated in the test time slot.
It is also possible to check the transmitting and receiving functions of the transmitting and receiving circuits by writing the S bit from the control device to the transmitting circuit and reading the S bit of the receiving circuit through the connection path according to the present invention to see if the transmitted and received S bits match. Become.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a multi-frame synchronization test method in a conventional time division switch, FIG. 2 is a diagram showing an embodiment of the multi-frame synchronization test method according to the present invention, and FIG. 3 is a diagram showing signals of each part of FIG. 2. This is a time chart showing. 100...Inter-station supervisory signal transmission circuit (SSS), 1
01...Inter-station monitoring signal receiving circuit (SSR), 102
...Time division communication channel, 103...Digital transmission line (HW), 104...Control device (CNT), 105...
...Digital signal device, 100'... Inter-office monitoring signal transmitting section, 101'... Inter-office monitoring signal receiving section, 1
06,109...2-1 selector (SEL), 10
7...8-bit shift register (SR), 108...
...gate, 110...connection path.

Claims (1)

[Scope of Claims] 1. A digital signaling device for a time-division exchange that transmits and receives inter-office monitoring signal bits in a multi-frame format, wherein the digital signaling device transmits inter-office monitoring signals of a highway line accommodated in a time-division communication path. an inter-office monitoring signal transmitter, an inter-office monitoring signal receiving section, and an inter-office monitoring signal receiving section for multiplexing the inter-office monitoring signals of the highway line, and transmitting the inter-office monitoring signals of the highway line to predetermined bit positions time-division multiplexed in a multi-frame format, and creating a multi-frame pattern. The inter-office monitoring signal transmitting section includes an inter-office monitoring signal transmitting circuit that transmits a signal consisting of a multi-frame pattern signal d including a test time slot, and the above-mentioned transmitting signal and a first select signal. a selection means for selecting the transmission signal based on the selection signal; and a selection means for selecting the transmission signal based on the selection signal;
and means for outputting a signal e containing the signal content of the time slot, and the inter-office monitoring signal receiving section outputs the signal e sent from the time division communication channel, the cyclic signal content, and a second select signal. means for selecting the content of the cyclic signal when the select signal is input, otherwise selecting the signal from the time-division channel, and absorbing the frame phase difference between the two signals e and f; , an inter-office monitoring signal receiving circuit that receives the output signal g of the absorption means, and a connection path that couples the circulating means of the inter-office monitoring signal transmitting section and the selection means of the inter-office monitoring signal receiving section; A multi-frame synchronization test method, characterized in that it includes means for setting and canceling a path, and enables an autonomous test of multi-frame synchronization within a digital signal device.