JPH0435940B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital exchange, and more particularly, to a digital exchange having a duplex switch module and a common interface section of a non-duplex line correspondence section.

In a digital switching system, in order to deal with failures in the switch module, this is duplicated.
One is used as a working switch and the other as a backup.
When a failure occurs in a module, a spare switch module is immediately switched to the active one to prevent any trouble in the operation of the exchange and to improve the reliability of the exchange.

On the other hand, in the digital exchange, a specific time slot of the corresponding highway is assigned for testing, test data is sent to the above test time slot on the downbound side of the paired highway, and test data is sent to the upstream highway test time slot. The communication path is tested by checking the test data sent back at the time slot and the data received back.

When performing the loopback test as described above on a switch with dual switch modules as described above, according to the conventional concept, only the active system side is tested, so it is difficult to check the normality of the standby system or troubleshooting problems. There is a problem with this.

FIG. 1 is a diagram showing the configuration of a digital exchange having a common interface section of a duplex switch module and a non-duplex line correspondence section.

In the figure, SHC ₀ to SHC _i are respectively interface common parts of the line corresponding parts, and SM ₀ and SM _i are switch modules, respectively, and both have the same configuration and are duplicated. is used as the active switch module, while the other one stands by as a standby, and if the active switch module becomes a failure, the standby switch module is switched to the active switch module.

Interface common part of line correspondence part SHC ₀ ~
SHC _i etc. are switch modules SM ₀ ,
Connected to SM ₁ by an interface highway. Since the interface common parts are configured similarly and operate similarly, SHC ₀ will be explained.

Digitized signals sent from telephones or lines are multiplexed in the line corresponding parts LINE ₀ to _{LINE o} and sent to the interface common part SHC ₀ .
It is further multiplexed into the up-highway FW-HW ₀ at the multiplexer MPX, divided into two, and each passes through the driver D to the up-highway FW-HW which is the interface highway.
Via HW ₀₀ and FW-HW ₁₀ , the switch modules SM ₀ and SM ₁ are reached, respectively.

Switch modules SM ₀ and SM ₁ exchange each other as described later, and are outputted from each via downbound highways BW-HW ₀₀ and BW-HW ₁₀ , which are interface highways. Ace common area
At SHC ₀ , each is received at receiver R and enters root selector RSEL.

The root selector RSEL is controlled by a root flip-flop R-FF which is controlled by the output of the signal reception distribution device SRD of the current switch module. That is, if the switch module SM ₀ is in use, the root flip-flop R-FF is set by the output of the signal reception distribution device SRD of the active switch module SM ₀ ;
Outputs “1”, which causes the root selector
Control the RSEL to control the current switch module
Downbound interface highway BW from SM ₀
- Select HW ₀₀ and connect it to the downbound highway BW-HW ₀ of the interface common section SHC ₀ . At this time, use the spare switch module SM _1.
Downbound Interface Highway BW−
HW ₁₀ data will be discarded.

At this time, if switch module SM ₁ is switched to the active one and switch module SM ₀ is switched to the spare one, the switch module that has become the active one
From the signal reception distribution device SRD of SM ₁ to the above route
A signal is applied to flip-flop R-FF to reset it. Then, the output of the root flip-flop R-FF becomes "0", and this output "0" causes the root selector RSEL to switch the input, and the currently used switch module SM ₁
Lower Interface Highway BW−
Select HW ₁₀ and interface common section SHC ₀
Connect to downbound highway BW-HW ₀ .

In the interface common section SHC ₀ , the signal of the downward highway BW-HW ₀ is separated into highways leading to the corresponding line corresponding section (LINE ₀ to LINE _o ) by a demultiplexer DMPX,
In each line corresponding section (LINE ₀ to _{LINE o} ), the call is further separated into incoming telephones or lines.

Since switch modules SM ₀ and SM ₁ each have the same configuration, switch module SM ₀ will be explained.

Switch Module SM ₀ is a multiplexer
MPX ₀ ~ MPX _o , demultiplexer DMPX ₀ ~
DMPX _o , forward time switch TSWF ₀ ~
TSWF _o , backward time switch TSWB ₀ ~
TSWB _o , spatial switch SSW, signal reception distribution device
Equipped with SRD etc. The two switch modules SM ₀ and SM ₁ are controlled by a common processor MPR.

As is well known, the time switch TSWF ₀ ~
The communication path holding memories in TSWF _o and TSWB ₀ to _{TSWB o} and the get control memory of the spatial switch SSW are controlled by signals from the signal reception and distribution device SRD, and a necessary communication path (speech channel) is set.

Interface common section SHC ₀ ~ Upbound interface highway FW-HW ₀₀ ~FW- from _{SHC i}
HW _0i is multiplexed by multiplexer MPX ₀ and input to forward time switch TSWF ₀ . SHC ₀ to
Similar to SHC _i , a considerable number, for example, i+1, are grouped together, and their upstream interface highways are input to multiplexers MPX ₁ to MPX _o . The multiplexed signal in the multiplexer MPX ₀ undergoes the necessary time slot conversion in the forward time switch TSWF ₀ and is input to the spatial switch SSW via the jack highway, where the conversion between the highways is performed and the backward time switch TSWF 0 is applied. It is input to TSWB ₀ to TSWB _o , is further subjected to time slot conversion, and sent to demultiplexers DMPX ₀ to DMPX _o , where it is sent to the required interface common part SHC ₀ to SHC _i .・Highway BW−HW ₀₀ ~
Separated into BW−HW _0i .

Inputs to the other multiplexers (MPX ₁ to MPX _o ) are processed in the same way as above.

As already mentioned, interface highways (FW-HW ₀₀ ~ etc. and BW-HW ₀₀ ~ etc. above)
etc.) for testing, the test data inserted into the test time slot is looped back, and the test is performed by comparing the sent data with the data received back. , in Fig. 1, the up and down highways FW-HW ₀ and BW-HW ₀ in the interface common section SHC ₀ are selected according to the conventional concept, and the test data is sent to the down highway in the test time slot. When testing the normality of the path through which the test data was transmitted by detecting a match between the test data and the test data returned to the up-bound highway, testing can only be performed from the active system, so the backup system backward time switch, especially the interface Since testing of the ace section could not be conducted, there were problems in fault isolation and system reconfiguration.

Further, this point will be explained in detail. 1st
As shown in the figure, in the interface common area SHC ₀ , the test data is transferred to the downbound highway BW-
It is assumed that the route returns from HW ₀ to the upbound highway FW-HW ₀ via the return route RR. In switch modules SM ₀ and SM ₁ , a backward time switch is selected from the spatial switch SSW, respectively.
Inserter I on Jankuta Highway leading to TSWB ₀ and forward time switch TSWF ₀
Dropper DR is installed on the junker highway leading to the spatial switch SSW, and the test data sent from the signal reception distribution device SRD is sent from the inserter I to the backward time switch TSWB ₀ , and the above loopback from the forward time switch TSWF ₀ is performed. The same test data was also used as a DR.
The configuration is such that the signal is taken out to the signal reception distribution device SRD via , and the two can be compared and verified.

For the loopback test, test data A of a specific pattern A (normally 8 bits are placed in one time slot _of the highway, so this test data is also 8 ) is sent from the signal reception distribution device SRD to the inserter I, inserted into a certain time slot, and inputted into the backward time switch _TSWB0 . the time switch
At TSWB ₀ , the time slots are exchanged so that the inserted test data is placed in the specific time slot TS ₀ allocated for the test of the interface highway BW-HW ₀₀ .

This test data is based on the route selector RSEL
After that, it appears at the test time slot TS ₀ on the downbound highway BW-HW ₀ . This test data is transferred to _the upbound highway FW-
It is looped back to HW ₀ , placed on time slot TS ₀ , and branches into two branches, one of which is connected to the multiplexer _{MPX 0 ,}
The signal reaches the dropper DR via the forward time switch TSWF ₀ and the juncture highway, where it is extracted and received by the signal reception and distribution device SRD. It is then further sent to the processor MPR,
Here, it is compared with the specific pattern A sent out earlier as test data.

The other one is a spare switch module SM ₁ .
Upbound interface/highway FW-
It is input from HW ₁₀ to the spare switch module SM ₁ , passes through the spare forward time switch TSWF ₀ , and is compared and matched exactly as in the working switch module SM ₀ .

In the conventional loopback test method described above, the backward time switch TSWB ₀ and the forward time switch TSWB 0 of the working system (SM ₀ ) where test data is transmitted are
The normality of the path including TSWF ₀ and interface common part SHC ₀ , and the backward time switch TSWB ₀ of the active system (SM ₀ ) and the backup system (SM ₁ )
The normality of the system including the forward time switch TSWF ₀ and the interface common section SHC ₀ is tested, but the backward time switch TSWB ₀ of the standby system (SM ₁ ) where test data is not transmitted cannot be tested. Even if an abnormality is detected, it is difficult to know which interface/highway the abnormality is located on.
Which switch module _{( SM 0 ,}
SM ₁ ) or which time switch (TSWF ₀ ... TSWB ₀ ..., etc.) it is located at, even if one could roughly guess, it was difficult to judge and confirm with high hardness.

In the conventional method, only the test data sent from the working switch module to the downbound interface highway (BW-HW ₀₀ ~, etc.) is sent to the working and standby switch modules on the downbound highway BW-HW ₀ ~ etc. Both modules were folded back. This is to avoid switching back-up equipment, which cannot necessarily be said to be operating stably, to current use, even if it is for testing purposes, while the exchange is in operation.
and the downbound interface highway from the spare switch module (BW-HW ₁₀ etc.)
All data sent above is route selector
Downbound highways are blocked at RSEL.
This is because it was difficult to turn back from BW−HW ₀ .

The present invention eliminates the above-mentioned drawbacks of the conventional system and eliminates the need to switch the standby unit to the working unit for repeat testing, and overcomes the above-mentioned difficulties. A digital switch with a standardized switch module is configured to be able to return test data sent from both the active and standby switch modules, making it possible to obtain a large amount of fault information. The purpose is to determine the location of the failure with even higher accuracy and to simplify and facilitate maintenance.

According to the present invention, the above object is achieved by providing a duplexed switch module, an interface common part of a non-duplexed line corresponding part, and a switch module.
It has an interface highway that connects each of the modules and the above-mentioned interface common part, and allocates a specific time slot of the above-mentioned interface highway as a return test time slot, and allows the switch module to use the above-mentioned time slot. In a digital exchange configured to perform a test by looping back the test data sent to the above interface common section, normally the test data is sent from the working switch module to the above test time slot and looped back with the test data. If an abnormality is detected as a result of the comparison, the current switch module sends instruction data to the test time slot from the backup switch module to select the test time slot. At the same time, a means for transmitting test data from the spare switch module and comparing the test data with the returned data is provided, and the interface common section also includes a timer for testing the interface highway from the working switch module.・Discrimination means for determining whether or not the content of the slot is the above-mentioned instruction data; and if the above-mentioned discrimination means determines that the content is not the above-mentioned instruction data, a time slot for testing the interface highway from the current switch module; The content is returned to the interface highway to the working and standby switch modules, and if it is determined by the above discrimination means to be the above instruction data, the test time of the interface highway from the standby switch module is returned.
and folding means for switching the contents of the slots back to the interface highway to the active and standby switch modules.

Next, the present invention will be explained with reference to the drawings.

The present invention is implemented in a digital exchange in which _the interface common parts SHC ₀ to SHC _i of _the line corresponding parts shown in FIG. And the second
The figure shows an example of the configuration of an interface common part of a line corresponding part in which the present invention can be implemented.

In Figure 2, MPX, DMPX, RSEL, R
-FF, D, and R are the same as in FIG. Note that SEL is a selector, G is a gate, PM is a pattern matcher, REG ₁ and REG ₂ are registers, and RS route selector. The input terminal _TS0 is supplied with an input during the test time slot _TS0 , thereby controlling the selector SEL and activating the registers _REG1 and _REG2 .

If the switch module SM ₀ is currently in use, the root flip-flop R-
FF is set, the route selector RSEL selects the down interface highway BW-HW ₀₀ from the working switch module SM ₀ , and is connected to the down highway BW-HW ₀ .
Since no input is given to the input end TS ₀ at times other than the test time slot TS ₀ , the selector SEL selects the upstream highway FW-HW ₀ from the multiplexer MPX and connects it to the two drivers D. do.

Therefore, the signals sent from the line corresponding parts (LINE ₀ to _{LINE o} ) are multiplexed to the uplink highway FW-HW ₀ by the multiplexer MPX, and sent to the working and standby switch modules via the selector SEL, as described above. Upbound interface highways FW-HW ₀₀ and FW-HW ₁₀ to SM ₀ and SM ₁
and input to each switch module SM ₀ and SM ₁ .

Working and spare switch module SM ₀ ,
The outputs exchanged in SM ₁ are the downstream interface highway BW-HW ₀₀ and BW-HW ₁₀
However, the route selector RSEL passes only the signal from the down interface highway BW-HW 00 from the working switch module SM ₀ , and outputs the signal from the down interface highway BW-HW ₀₀ from the backup switch module SM ₁ . BW−HW ₁₀
Blocking signals from other sources.

As described above, the signal sent to the downbound highway BW-HW ₀ on the output side of the route selector RSEL is separated by the demultiplexer DMWPX and sent to a predetermined line corresponding section (LINE ₀ to _{LINE o} ). .

Here, the return means that can be switched to return the test data sent from the standby switch module to both the active and standby switch modules according to instructions from the active switch module include a route selector RS and a register REG. ₁ ,
REG ₂ , pattern matcher PM and gate G
It consists of

The test data (pattern A) sent from the above-mentioned working switch module SM ₀ is returned as follows.

As mentioned above, the current switch module
Downbound interface highway BW from SM ₀
- The test data sent in test time slot TS ₀ of HW ₀₀ is route selector RSEL.
and is sent to the downbound highway BW-HW ₀ .
When a signal is applied to the input terminal TS ₀ at the time of the test time slot TS ₀ , the register REG ₁
is activated, and on the downbound highway BW−HW ₀ ,
The test data (pattern A) at the relevant time (time slot TS ₀ ) is stored in the register REG ₁ . At this time, the contents of register REG ₁ are different from the comparison target of pattern matcher PM, so pattern matcher PM does not send out an output, and gate G passes the contents of register REG ₁ and outputs it. controlled. At the next time slot TS ₀ , when selector SEL is activated, register
The contents of REG ₁ , that is, the test data (pattern A) pass through gate G and selector SEL to the working and standby switch modules SM ₀ and SM ₁ on the uplink interface highway FW-HW _00.
and FW-HW ₁₀ , respectively. In this way, the test data has already been folded back as described with reference to FIG.

If an abnormality is detected in the above return test,
According to the present invention, instead of the above, test data is sent from the standby switch module SM ₁ to its downbound interface highway BW-HW ₁₀ , and this test data is sent to the working and standby switch modules SM ₀ and SM _1. The test shall be carried out by returning to the office.

As explained with reference to FIG. 1, in the conventional loopback test described above, if the processor MPR detects an abnormality, the processor MPR transfers the test data to the test time slot TS ₀ for the backup switch module SM ₁ . It also instructs the current switch module _SM0 to transmit a specific pattern of instruction data (pattern B) to the test time slot _TS0 . As a result, the test and instruction data are sent to the down interface highways BW-HW ₁₀ and BW-HW ₀₀ , respectively, in the same manner as described in FIG.

Now, in Figure 2, the root selector RS
is controlled by the output of the root flip-flop R-FF and, contrary to the root selector RSEL, blocks signals on the downbound interface highway from the working switch module and blocks signals on the downbound interface highway from the standby switch module.・
Pass traffic lights on the highway. That is, in this case, the signal from the downlink interface highway BW-HW ₁₀ from the backup switch module SM ₁ is passed through and sent to the register REG ₂ .

At the time of the test time slot TS ₀ , when an input is applied to the input terminal TS ₀ , the register REG ₂ is activated, and the downlink interface highway BW-HW ₁₀ from the backup switch module SM ₁ is activated.
The test data (pattern A) placed in the test time slot _TS0 is latched into the register _REG2 .

At this time, the specific pattern of instruction data (pattern B) sent from the working switch module SM ₀ to the test time slot TS ₀ of the down interface highway BW-HW ₀₀ is the same as above. is latched into register REG ₁ . This content (pattern B data) is sent to the pattern matchmaker PM, and the pattern matcher
When it is compared and verified in PM and it is identified as pattern B, a signal is sent to gate G, which blocks the passage of the signal with the contents of register REG ₁ and blocks the passage of the signal with the contents of register REG ₂ . Switched to pass. Next exam time/
When the selector SEL is switched in the slot TS ₀ , the contents of the register REG ₂ , that is, the test data sent from the downlink interface highway BW-HW ₁₀ from the backup switch module SM ₁ are transferred to the current and Upstream interface highway FW to spare switch modules SM ₀ and SM ₁ - HW ₀₀ and FW -
Sent to HW ₁₀ . The instruction data shall have a different pattern from the test data. Note that the instruction data is not limited to a specific pattern. For example, bits at specific bit positions may be assigned.

This returned test data is used for the current and backup switch modules SM ₀ ,
In each SM ₁ , the data is extracted by the dropper DR, reaches the signal reception distribution device SRD, and is further sent to the processor MPR, where the transmitted test data is compared with the received data, and the transmitted test data is Path health is detected.

To summarize the loopback test method for the digital switch of the present invention described above, first,
The test data sent via the downbound interface highway (BW-HW ₀₀ ) from module SM ₀ is sent to the interface common section SHC ₀ .
Inbound interface highways (FW _{-HW 00 ) and (FW-HW 10 )} to working switch module SM ₀ and standby switch module SM ₁
If the normality of each path is detected, and an abnormality is detected in at least _one of the・Highway (BW-HW ₁₀ )
The test data is sent via the uplink interface highway (FW-HW ₀₀ ) and (FW-HW ₁₀ ) to the working switch module SM ₀ and standby switch module SM ₁ in the same way as above.
The normality of each route is detected.

In the loopback test described above, in which test data is sent from the working system and received by the working system and the protection system, (a) If the test data is successfully received by both the working system and the protection system, the working system Backward time switch TSWB ₀ , forward time switch
TSWF ₀ and interface common section SHC ₀ are normal (protection system is forward time switch
Only TSWF ₀ is normal).

(b) If the test data is normally received on only one of the active system or the backup system, it is determined that the forward time switch of the system that was not properly received is defective.

(c) If the test data is not received normally on both systems, it is determined that the working system's backward time switch, the interface common section, or the respective forward time switches of both the working and standby systems are defective.

Furthermore, in the loopback test in which the above test data is sent from the backup system and received by the working system and the backup system, (d) If the test data is successfully received by both the working system and the backup system, then the backup System backward time switch TSWB ₀ and interface common section SHC ₀ are determined to be normal.

(e) Same as (b) above.

(f) If the test data is not received normally on both systems, it is determined that the backup system's backward time switch, the interface common section, or the respective forward time switches of both the active and backup systems are defective.

Furthermore, the processor MPR processes the information obtained as a result of the above tests using a program, and
Determine which location, such as the forward time switch or the backward time switch, is at fault.

The present invention is not limited to the above embodiments, and various modifications can be made within the technical scope thereof.
Conventionally, in digital exchanges that have an interface common part of the non-duplicated line compatible part and a duplicated switch module, test data is sent from the active switch module and used in the interface common part mentioned above. A loopback test was conducted on both the switch module and the backup switch module, but the information regarding normality and abnormality of the interface section between the common interface section and the duplicated switch module is as described above. Although it was possible to estimate the location of the failure from the above test results, it was not possible to identify it with a high degree of accuracy. According to the present invention, in addition to the above-mentioned conventional loopback test, a loopback test similar to the above is performed by sending test data from a spare switch module, so that normality at the interface section and other parts can be determined. A large amount of information regarding the abnormality can be obtained, which makes it possible to isolate the location of the failure with higher accuracy than in the conventional method, and has the effect of simplifying and facilitating the maintenance of this type of exchange. Furthermore, since it is possible to test a switching equipment that is in operation without switching over to the active switch module, which cannot necessarily be said to operate stably, this test has the advantage that it does not adversely affect the operation of the switching equipment. .

[Brief explanation of drawings]

FIG. 1 is a connection configuration diagram of an example of a conventional digital exchange with dual switch modules capable of implementing the present invention, and FIG. 2 is a common interface section of a line corresponding section for implementing the present invention. It is a connection diagram of an example. SHC ₀ ~ SHC _i ...Interface common part of the line support section, SM ₀ , SM ₁ ...Duplicated switch
Module, MPR...Processor, MPX,
MPX ₀ ~ MPX _o ……Multiplexer, DMPX,
DMPX ₀ ~ DMPX _o ...Demultiplexer, D...
...Driver, R...Receiver, RSEL...Root selector, R-FF...Root flip-flop, TSWF ₀ to TSWF _o ...Forward time switch, TSWB ₀ to TSWB _o ...Backward time switch, SSW...Space Switch, SRD...
Signal reception distribution device, DR...Dropper, I...Inserter, REG ₁ , REG ₂ ...Register, RS...
Route selector, SEL...selector, G...gate, PM...pattern matsutiya.

Claims (1)

[Scope of Claims] 1. A duplexed switch module, an interface common part of a non-duplicated line corresponding part, and an interface that connects each of the switch modules and the interface common part. The above-mentioned interface/
In a digital switch that is configured to allocate a specific time slot on the highway as a loopback test time slot, and perform a test by looping back the test data sent from the switch module to the above time slot at the above interface common section, The test data is sent from the current switch module to the above test time slot, and the test data is compared with the returned data. If an abnormality is detected as a result of the comparison, the test data is sent from the current switch module to the above test time slot. Means for causing the time slot to transmit instruction data from the backup switch module to select the test time slot, and for causing the backup switch module to transmit test data and comparing the test data with the returned data. In addition, the interface common part is provided with a determining means for determining whether or not the contents of the interface highway test time slot from the current switch module correspond to the above instruction data; If it is determined that it is not data, the content of the test time slot of the interface highway from the working switch module is returned to the interface highway to the working and standby switch modules, and the above-mentioned instruction data is determined by the above-mentioned discrimination means. If it is determined that there is an interface highway test time from the spare switch module.
1. A digital switch, characterized in that it is provided with return means for switching the contents of the slot back to the interface highway to the active and standby switch modules.