JPS62180650A - Line state supervising equipment - Google Patents

Abstract

PURPOSE:To reduce ineffective processing time while making the processing capability of a controller independent of the number of bits by allowing a host controller to read a line state change holding circuit periodically, supervising change detection information subjected to bit multiplexing and reading the line state of a line whose change detection information corresponds to the bit. CONSTITUTION:A line state display signal extraction circuit 10 extracts a line state display signal of a present period from an input signal fed to an input terminal 1 and gives the display signal to a line state holding circuit 20 and a line state change detection circuit 30. The line state holding circuit 20 holds the line state display signal for one period and outputs the signal to the line state change detection circuit 30 as a line state display signal of the preceding period at the next period. The line state change detection circuit 30 compares the line state display signals between the present period and the preceding period to detect the change in the line state nd outputs change detection information to a line state change detection holding circuit 40 at the detection change. The line state change detection holding circuit 40 at the detection change. The line state change detection holding circuit 40 holds the change detection information as a change detection flag and when a read command is received from an input terminal 2a, and the change detection flag information corresponding to the read command information is outputted to an output terminal 2b.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] ' □Thursday The invention relates to a line status monitoring device that displays the line status using a plurality of bits for each line.

[Prior Art] Conventionally, this type of device periodically extracts and monitors n bits for each line by software processing.

Now, let the number of status display pids for each line be n□, the number of lines be
If the number of status display bits that can be read at one time is M, and the number of read results and storage memory □ bits in period □ is M bits, then when IXL n=1, the number of line status readings - □.

[Problem that the invention seeks to solve]

The conventional line status monitoring device described above performs reading monitoring periodically through software processing, so the number of line status readings and the number of status change detection processes (program processing amount) increases almost in proportion to the number of bits n. , the time that the blockrum occupies the control device also increases in proportion to the number of bits n, which has the disadvantage of putting pressure on the processing capacity of the control device.Also, considering the case where we make a telephone call, the line state changes As can be easily inferred, it does not occur very often, so even if the time occupied by the program's control device increases in proportion to the number n, it does not increase when detecting line state changes. , there is a drawback that the invalid processing time of the control device increases.

1.1 of the present invention is to provide a line status monitoring device in which when the line status is displayed using n bits, the processing capacity of the control unit does not depend on the number of bits n, and the invalid processing time of the control unit is reduced. It is in.

[Failure to solve the problem]

The line status monitoring device of the present invention includes a line status table non-signal extracting circuit that extracts the line status display signal of the current cycle from the input signal, and a line status display signal of all lines that is held for one cycle, and the line status display signals of the previous cycle are stored in the next cycle. When a line status read command is received from a higher-level control device, a line status holding circuit outputs the held contents of the corresponding line, and a line status display signal for each line is output in sequence. A line state change detection circuit detects a change in line state by simultaneously receiving the line state display signal of the same line in the previous cycle from the line state holding circuit; Equipped with a memory that retains the presence or absence of a change in the state of each line as an output, and when a change in line state is detected, change detection information is set in the memory, and the information in the memory is output according to the read instruction information from the higher-level control device, and the higher-level control When an instruction to read the line status of a line corresponding to change detection information from the device is issued, the apparatus includes a line status change holding circuit that releases the change detection information held until then.

Therefore, in order to monitor the line status display with n bits, it is only necessary to monitor the bit-multiplexed change detection information and read only the line status with n bits corresponding to the bit where the change detection information is set. Therefore, the processing amount of the program that performs the state change detection process is not proportional to the number of bits n, but is a substantially constant value.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

Figure 1 is CC, ITT G, 732. A block diagram showing an embodiment of the line status monitoring device of the present invention applied to the R2 signaling system line signal digital version recommended in Q421, FIG. 2(A) is the input terminal 1 in FIG.
With the human-powered highway information added to CCITT G,
A diagram of the 2,048 M b/s input signal recommended in G.732 and the line status display signal extracted from the input signal,
1 (B) shows the contents of the state holding memory of the line state holding circuit 20 in FIG. 1, and (C) shows the change detection flag of the line state change detection holding circuit 40 in FIG. 1. FIG. 2 is a diagram showing the contents of a memory.

The line status display signal extraction circuit 10 extracts the line status display signal of the current cycle from the input signal applied to the input terminal 1, and outputs it to the line status holding circuit 20 and the line status change detection circuit 30. The line state holding circuit 20 holds the line state display signal for one cycle and outputs it to the line state change detection circuit 30 in the next cycle as the line state display signal of the previous cycle. The line state change detection circuit 30 detects a change in line state by comparing corresponding line state display signals between the current cycle and the previous cycle.
When a change is detected, change detection information is output to the line state change detection and holding circuit 40. The line state change detection and holding circuit 40 holds the change detection information as a change detection flag, and stores the change detection information as a change detection flag.
When receiving a read instruction from , it outputs change detection flag information corresponding to the read instruction information to the output terminal 2b. The line state change detection and holding circuit 40 further holds the line state read instruction for the line corresponding to the change detection flag until it receives from the input terminal 3a, and then releases the change detection flag.

Further, when the line state holding circuit 20 receives a line state read instruction from the input terminal 3a, it outputs line state information corresponding to the read instruction information to the output terminal 3b.

Next, the operation of this embodiment will be explained with reference to FIG.

When the highway information shown in FIG. 2 (8) is manually input from the input terminal 1, the line status display signal extraction circuit 10 extracts a line status signal (line signal) from the TS 16, and the line status holding circuit 20 and the line status change detection circuit 10 extract the line status signal from the TS 16. to the circuit 30. The line state holding circuit 20 holds the transmitted line signal in a state holding memory within the circuit in the form shown in FIG. 2(B).

Therefore, the higher-level control device can freely read the contents of the holding memory, that is, the line status, via the input terminal 3a and the output terminal 3b. The line state change detection circuit 30 compares the line signal of the multi-frame of the current cycle with the line signal of the multi-frame of the previous cycle corresponding to the line signal of the multi-frame of the current cycle, each 4 bits (abcd), and changes if they do not match. The detection information is transferred to the line state change detection and holding circuit 40.
The line state change detection and holding circuit 40 holds the change detection flag in the internal change detection flag memory in the form shown in FIG. 2(C). Therefore, the host control device periodically reads out the change detection flag memory contents, that is, the bit-multiplexed change detection flag, via the input terminal 2a and output terminal 2b, and inputs it only to the line where the change detection flag is set. The line status can be monitored by reading the line status via the terminal 3a and output terminal 3b. Since the probability of detecting the setting of the detection flag is low, the time taken to read out the line status is extremely small compared to the time taken to read out the change detection flag.

〔Effect of the invention〕

As explained above, in the present invention, a host control device periodically reads the line state change holding circuit, monitors bit-multiplexed change detection information, and furthermore, the control device periodically reads the line state change holding circuit, monitors the bit-multiplexed change detection information, and By reading the line status,
Since the line status display with the number of bits n can be monitored, the processing amount of the program that is periodically activated to read the line status and detect status changes is not proportional to the number of bits n, and is approximately constant, so the program occupies the control device. The processing time is not proportional to the number of bits n, but is approximately constant, which has the effect of not putting pressure on the processing capacity of the control device, and further has the effect of minimizing the invalid processing time of the control device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the line condition monitoring device of the present invention, and FIG. 2 (A) shows the input signal applied to the input terminal 1 of FIG. 1 and the line condition extracted from the thermal signal. A diagram of the display signal, (B) is the line status holding circuit 40 of FIG.
(C) shows the contents of the memory that holds the change detection flag of the line state change detection and holding circuit 40 of FIG. 20...Line status holding circuit, 30---Line status change detection circuit, 40...
...Line state change holding circuit, 1... Signal input terminal, 2a, 3a... Read instruction information input terminal, 2
b-... Change detection information output terminal, 3b...
- Line status information output - child.

Claims (1)

[Claims] A line status monitoring device that monitors multiple bits for each line as a line status display signal in an input signal in which the signals of each line are time-division multiplexed, A line status display signal extraction circuit that extracts a line status display signal, holds the line status display signal for one cycle, outputs it as the line status display signal of the previous cycle in the next cycle, and receives a line status read command from the host controller. When received, the line status holding circuit outputs the held contents of the corresponding line, and the line status display signal extraction circuit receives the line status display signal of each line sequentially, and at the same time displays the line status of the same line in the previous cycle. It is equipped with a line state change detection circuit that receives signals from the line state holding circuit and detects changes in the line state, and a memory that retains the presence or absence of changes in each line state that is the output of the line state change detection circuit. At the time of detection, the change detection information is set in the memory, and the information in the memory is output according to the read instruction information from the upper control device, and when the line status read instruction of the line corresponding to the change detection information is issued from the upper control device , and a line state change holding circuit for canceling the change detection information held until then.