JPS6093502A - Output holding system of digital controller - Google Patents

Output holding system of digital controller

Info

Publication number
JPS6093502A
JPS6093502A JP20207283A JP20207283A JPS6093502A JP S6093502 A JPS6093502 A JP S6093502A JP 20207283 A JP20207283 A JP 20207283A JP 20207283 A JP20207283 A JP 20207283A JP S6093502 A JPS6093502 A JP S6093502A
Authority
JP
Japan
Prior art keywords
output
register
fault
time
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP20207283A
Other languages
Japanese (ja)
Inventor
Koshu Narihara
成原 弘修
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP20207283A priority Critical patent/JPS6093502A/en
Publication of JPS6093502A publication Critical patent/JPS6093502A/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/20Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Safety Devices In Control Systems (AREA)

Abstract

PURPOSE:To secure a minimum necessary output state without placing an output signal in an abnormal state even in case of a fault by providing a fault-time output register, and setting the same data with a normal-time output register therein periodically. CONSTITUTION:The fault-time output register 3 is provided in addition to the normal-time output register 2, and the same data is set periodically. If the output register 2 gets out of order or if the data in the register 2 is destroyed, a fault detecting circuit 5 generates a fault-time switching signal, an output switching circuit 4 selects the data in the fault-time register 3, and an output circuit 6 outputs an output signal from a terminal. Thus, the fault-time output register 3 is provided to maintain a minimum necessary output state without putting the output signal in an abnormal state even in case of a fault, so damage to a process to be controlled is prevented.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は、ディジタル制御装置の故障時においても制
御対象に対して最低限必要な出力状態を維持できるよう
にしたディジタル制御装置の出力保持方式に関する。
[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to an output holding method for a digital control device that makes it possible to maintain the minimum required output state for a controlled object even when the digital control device fails. .

〔従来技術〕[Prior art]

従来、この種の方式としては第1図のものがあった。1
はマイクロプロセッサ、2はディジタル信号をセットす
る出力レジスタ、6は出力レジスタに保持されているデ
ータを出力する出力回路である。
Conventionally, there has been a system of this type as shown in FIG. 1
2 is an output register for setting digital signals, and 6 is an output circuit for outputting data held in the output register.

次に動作について説明する。マイクロプロセラt1は、
周期的に出力レジスタ2にディジタル信号をセットし、
出力すべきデータを更新する。出力回路6は上記出力レ
ジスタ2に保持されているデータを出力し、出力端子よ
シ出力信号が取出せる。
Next, the operation will be explained. MicroProcera t1 is
Periodically set a digital signal to output register 2,
Update the data to be output. The output circuit 6 outputs the data held in the output register 2, and an output signal can be taken out from the output terminal.

従来の出力保持方式では、出力レジスタ2のデータがそ
のまま出力されていたので、出力レジスタ2が故障する
か、または出力レジスタ2のデータが破壊された場合、
出力が異常になる事態を招来するという欠点があった。
In the conventional output holding method, the data in the output register 2 is output as is, so if the output register 2 fails or the data in the output register 2 is destroyed,
This has the drawback of causing a situation where the output becomes abnormal.

特にディジタル制御装置においては、アナログ制御装置
のように外乱に対し自動的に元の正常な状態に復帰する
のに対して復帰しにくいため異常出力はプロセスに重大
な被害をおよぼすことがある。このため、その異常用力
を瞬時に監視し、故障発生時にもプロセスに対して大き
な変化を招来させない様に構成することが要請されてい
る。
In particular, in a digital control device, unlike an analog control device, which automatically returns to the original normal state in response to a disturbance, it is difficult to return to the original state, so abnormal output may cause serious damage to the process. For this reason, there is a need for a system that can instantly monitor abnormal power consumption and prevent major changes in the process even when a failure occurs.

〔発明の概要〕[Summary of the invention]

この発明は上記のような従来のものの欠点を除去するた
めになされたもので、故障時においても出力信号が異常
状態になるのを防ぎ、最低限必要な出力状態を確保する
ディジタル制御装置の出方保持方式を提供することを目
的としている。
This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and it is a digital control device that prevents the output signal from going into an abnormal state even in the event of a failure and ensures the minimum required output state. The purpose is to provide a method for maintaining

(発明の実施例〕 以下、この発明の実施例を図について説明する。(Example of the invention) Embodiments of the present invention will be described below with reference to the drawings.

第2図において、lはマイクロプロセッサ、2は正常時
に出力すべきデータを格納しておく出力レジスタ、3は
故障時に出力すべきデータを格納しておく故障時出力レ
ジスタ、4は上記出力レジスタ2と上記故障時出力レジ
スタ3のデータを選択的に出力する出力切換回路、5は
出方切換回路4を切シ換えるだめの切シ換え信号を発生
する故障検出回路、6は上記出力切換回路で選択された
出力を出す出力回路である。
In FIG. 2, l is a microprocessor, 2 is an output register that stores data that should be output during normal operation, 3 is a failure output register that stores data that should be output in the event of a failure, and 4 is the output register 2. 5 is a failure detection circuit that generates a switching signal to switch the output switching circuit 4, and 6 is the output switching circuit. This is an output circuit that outputs a selected output.

次に動作について説明する。マイクロプロセッサ1は、
周期的に出力レジスタ2および故障時出力レジスタ3に
ディジタル信号をセットし、出力すべきデータを更新す
る。正常時には、出力レジスタ2に保持されているデー
タが出力切換回路4を通して出力回路6によシ出力端子
から出力信号が取出せる。この時、出力レジスタ2が故
障するかまたは出力レジスタのデータが破壊された場合
、故障検出回路5によシ故障時切換信号が発生し、故障
時出力レジスタ3のデータが出力切換回路4で選択され
、出力回路6によシ出力信号が端子から出力される。
Next, the operation will be explained. Microprocessor 1 is
Digital signals are periodically set in the output register 2 and the failure output register 3 to update the data to be output. During normal operation, the data held in the output register 2 is passed through the output switching circuit 4 to the output circuit 6, and an output signal can be taken out from the output terminal. At this time, if the output register 2 fails or the data in the output register is destroyed, the failure detection circuit 5 generates a failure switching signal, and the data in the failure output register 3 is selected by the output switching circuit 4. The output circuit 6 outputs an output signal from the terminal.

出力レジスタ2および故障時出力レジスタ3に周期的に
同一データをセットするようにしておけば、出力レジス
タ2のデータが破壊された場合でも故障前のデータが出
力されることになる。
If the same data is periodically set in the output register 2 and the failure output register 3, even if the data in the output register 2 is destroyed, the data before the failure will be output.

第3図はこの発明の他の実施例によるディジタル制御装
置の出力保持方式のブロック図である。
FIG. 3 is a block diagram of an output holding system for a digital control device according to another embodiment of the present invention.

第3図において、2は出力レジスタ、4は出力切換回路
、6は出力回路、7は切換信号発生回路である。第2図
の実施例では、故障検出回路5で検出した故障時切換信
号で出力切換回路4を切シ換えているのに対して、第3
図の実施例では任意の切換信号発生回路の出力信号で出
力回路4を切シ換えている。また切シ換える出力信号数
は2点に限らず、多点出力の切シ換えも可能である。さ
らにマイクロプロセッサは必ずしも必要でなく、出力レ
ジスタにデータがセットできる構成のものであれば、デ
ィジタル制御部が如何なる構成を有するものでも良い。
In FIG. 3, 2 is an output register, 4 is an output switching circuit, 6 is an output circuit, and 7 is a switching signal generating circuit. In the embodiment shown in FIG. 2, the output switching circuit 4 is switched by the fault switching signal detected by the fault detection circuit 5, whereas the third
In the illustrated embodiment, the output circuit 4 is switched by an output signal from an arbitrary switching signal generating circuit. Further, the number of output signals to be switched is not limited to two, and switching of multiple outputs is also possible. Further, a microprocessor is not necessarily required, and the digital control section may have any configuration as long as it can set data in the output register.

〔発明の効果〕〔Effect of the invention〕

以上のように、この発明によれば、故障時においてもデ
ィジタル制御装置の出力信号が異常になることなく、最
低限必要な出力状態を維持することができるので、制御
対象プロセスに対して重大な被害を招来させずに制御で
きる効果がある。
As described above, according to the present invention, even in the event of a failure, the output signal of the digital control device does not become abnormal, and the minimum required output state can be maintained, so that it is possible to maintain the minimum required output state. It has the effect of being able to control it without causing any damage.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来のディジタル制御装置の出力保持方式を示
すブロック図、第2図はこの発明の一実施例によるディ
ジタル制御装置の出力保持方式を示すブロック図、第3
図はこの発明の他の実施例によるディジタル制御装置の
出力保持方式を示すブロック図である。 1・・・マイクロプロセッサ、2・・・出力レジスタ、
3・・・故障時出力レジスタ、4・・・出力切換回路、
5・・・故障検出回路、6・・・出力回路、7・・・切
換信号発生回路。 なお、図中同一符号は同一部分を示す。 代理人 大岩増雄 手続補正書(自発) 1.事件の表示 特願昭 58−202072号2、発
明の名称 ディジタル制御装置の出方保持方式 3、補正をする者 代表者片山仁へ部 4、代理人 5、補正の対象 明細書の発明の詳細な説明の欄 6、補正の内容 明細書第4頁第6行目「を通して」とあるのを「で選択
され、」と補正する。 以上
FIG. 1 is a block diagram showing an output holding method of a conventional digital control device, FIG. 2 is a block diagram showing an output holding method of a digital control device according to an embodiment of the present invention, and FIG.
The figure is a block diagram showing an output holding system of a digital control device according to another embodiment of the present invention. 1... Microprocessor, 2... Output register,
3...Failure output register, 4...Output switching circuit,
5... Failure detection circuit, 6... Output circuit, 7... Switching signal generation circuit. Note that the same reference numerals in the figures indicate the same parts. Agent Masuo Oiwa Procedural Amendment (Voluntary) 1. Indication of the case: Japanese Patent Application No. 58-202072 2, Title of the invention: Digital control device appearance retention system 3, Person making the amendment Representative Hitoshi Katayama Department 4, Agent 5, Details of the invention in the specification to be amended Explanation column 6, page 4, line 6 of the description of the contents of the amendment, ``through'' is amended to ``selected by''. that's all

Claims (1)

【特許請求の範囲】[Claims] ディジタル制御装置の正常時の出方データを保持する出
力レジスタと、上記ディジタル制御装置の故障時の出力
データを保持する故障時出力レジスタと、上記出力レジ
スタ又は故障時出力レジスタの各データのいずれかを選
択する出力切換回路と、この出力切換回路に故障時切換
信号を供給する故障検出回路と、上記出力切換回路の出
力データを出力する出力回路とを備えたディジタル制御
装置の出力保持方式。
An output register that holds the output data of the digital control device during normal operation, an output register at the time of failure that holds the output data of the digital control device at the time of failure, and each data of the above-mentioned output register or output register at the time of failure. An output holding system for a digital control device comprising: an output switching circuit that selects an output switching circuit; a failure detection circuit that supplies a fault switching signal to the output switching circuit; and an output circuit that outputs output data of the output switching circuit.
JP20207283A 1983-10-26 1983-10-26 Output holding system of digital controller Pending JPS6093502A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20207283A JPS6093502A (en) 1983-10-26 1983-10-26 Output holding system of digital controller

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20207283A JPS6093502A (en) 1983-10-26 1983-10-26 Output holding system of digital controller

Publications (1)

Publication Number Publication Date
JPS6093502A true JPS6093502A (en) 1985-05-25

Family

ID=16451481

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20207283A Pending JPS6093502A (en) 1983-10-26 1983-10-26 Output holding system of digital controller

Country Status (1)

Country Link
JP (1) JPS6093502A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS626302A (en) * 1985-07-03 1987-01-13 Fuji Electric Co Ltd N:1 back-up system
JPH01134604A (en) * 1987-11-20 1989-05-26 Mitsubishi Electric Corp Programmable controller
JPH0356391A (en) * 1989-07-21 1991-03-11 Hitachi Ltd Passenger conveyor control device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS626302A (en) * 1985-07-03 1987-01-13 Fuji Electric Co Ltd N:1 back-up system
JPH01134604A (en) * 1987-11-20 1989-05-26 Mitsubishi Electric Corp Programmable controller
JPH0356391A (en) * 1989-07-21 1991-03-11 Hitachi Ltd Passenger conveyor control device

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