JPS56140443A - Microprogram initial diagnostic system - Google Patents

Microprogram initial diagnostic system

Info

Publication number
JPS56140443A
JPS56140443A JP4177380A JP4177380A JPS56140443A JP S56140443 A JPS56140443 A JP S56140443A JP 4177380 A JP4177380 A JP 4177380A JP 4177380 A JP4177380 A JP 4177380A JP S56140443 A JPS56140443 A JP S56140443A
Authority
JP
Japan
Prior art keywords
mupr
initial diagnosis
address
microprogram
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4177380A
Other languages
Japanese (ja)
Inventor
Tetsuo Isaka
Tadahiro Wada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP4177380A priority Critical patent/JPS56140443A/en
Publication of JPS56140443A publication Critical patent/JPS56140443A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

Abstract

PURPOSE:To prevent the routine from jumping outside the microprogram muPR area for initial diagnosis, by fixing forcibly a part of address register AR while muPR for initial diagnosis is executed. CONSTITUTION:When the execution command of muPR for initial diagnosis is transferred to address control part 3, control part 3 sets a prescribed address to AR4, and the diagnostic routine start instruction is issued from control memory 1 and is set to output register 2. Decoder 5 decodes the prescribed address of AR4 and sets so that 0 is output to diagnosis instructing FF8 through OR circuit 6. As the result, upper bits of AR4 are set to 0 forcibly, and the address indicated by AR4 indicates only the part in the area of muPR for initial diagnosis even in case of the occurrence of an accident in a part of AR4 while muPR for initial diagnosis is executed. When said muPR has terminated and the diagnostic routine end instruction is read out, 1 is output to OR circuit 7 by decoder 5, and FF8 is reset, and the forced fixing of upper bits of AR4 is released.
JP4177380A 1980-03-31 1980-03-31 Microprogram initial diagnostic system Pending JPS56140443A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4177380A JPS56140443A (en) 1980-03-31 1980-03-31 Microprogram initial diagnostic system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4177380A JPS56140443A (en) 1980-03-31 1980-03-31 Microprogram initial diagnostic system

Publications (1)

Publication Number Publication Date
JPS56140443A true JPS56140443A (en) 1981-11-02

Family

ID=12617696

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4177380A Pending JPS56140443A (en) 1980-03-31 1980-03-31 Microprogram initial diagnostic system

Country Status (1)

Country Link
JP (1) JPS56140443A (en)

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