JPS5613852A - Two-way data bus - Google Patents

Two-way data bus

Info

Publication number
JPS5613852A
JPS5613852A JP8941379A JP8941379A JPS5613852A JP S5613852 A JPS5613852 A JP S5613852A JP 8941379 A JP8941379 A JP 8941379A JP 8941379 A JP8941379 A JP 8941379A JP S5613852 A JPS5613852 A JP S5613852A
Authority
JP
Japan
Prior art keywords
mos
resistance
input
signal
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8941379A
Other languages
Japanese (ja)
Inventor
Satoru Koide
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP8941379A priority Critical patent/JPS5613852A/en
Publication of JPS5613852A publication Critical patent/JPS5613852A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L5/00—Arrangements affording multiple use of the transmission path
    • H04L5/14—Two-way operation using the same type of signal, i.e. duplex

Abstract

PURPOSE:To realize a direct connection between N-MOS and P-MOS devices, by connecting the C-MOS device to the input/output terminal of N-MOS and P-MOS devices each via the resistance and then giving the control to the signal transfer direction by the input signal. CONSTITUTION:Input/output terminals 1a and 2a of N-MOS and P-MOS devices 1 and 2 each are connected to two-way data bus main body 4 via resistance 3. And C-MOS buffer IC6 is connected to main body 4 via resistance 5. Signal transfer direction control signal TDS of e.g. 0V or -5V is supplied to the input of IC6. With supply of signal TDS of -5V to IC6, the output of device 2 is pulled down by resistance 5 to be received at device 1 in a correct way for both the high and low levels. And with application of signal TDS of 0V to IC6, the output of device 1 is pulled up by resistance 5 to be received at device 2 correctly for both the high and low levels.
JP8941379A 1979-07-13 1979-07-13 Two-way data bus Pending JPS5613852A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8941379A JPS5613852A (en) 1979-07-13 1979-07-13 Two-way data bus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8941379A JPS5613852A (en) 1979-07-13 1979-07-13 Two-way data bus

Publications (1)

Publication Number Publication Date
JPS5613852A true JPS5613852A (en) 1981-02-10

Family

ID=13969951

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8941379A Pending JPS5613852A (en) 1979-07-13 1979-07-13 Two-way data bus

Country Status (1)

Country Link
JP (1) JPS5613852A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59217295A (en) * 1983-05-24 1984-12-07 Seiko Instr & Electronics Ltd Complementary type electronic signal input circuit
JPS604055U (en) * 1983-06-20 1985-01-12 株式会社富士通ゼネラル Bidirectional interface circuit
US11450551B2 (en) 2019-09-16 2022-09-20 Ap Systems Inc. Edge ring and heat treatment apparatus having the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59217295A (en) * 1983-05-24 1984-12-07 Seiko Instr & Electronics Ltd Complementary type electronic signal input circuit
JPS604055U (en) * 1983-06-20 1985-01-12 株式会社富士通ゼネラル Bidirectional interface circuit
JPH0224293Y2 (en) * 1983-06-20 1990-07-03
US11450551B2 (en) 2019-09-16 2022-09-20 Ap Systems Inc. Edge ring and heat treatment apparatus having the same

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