JPS56134826A - Binary circuit - Google Patents
Binary circuitInfo
- Publication number
- JPS56134826A JPS56134826A JP3806680A JP3806680A JPS56134826A JP S56134826 A JPS56134826 A JP S56134826A JP 3806680 A JP3806680 A JP 3806680A JP 3806680 A JP3806680 A JP 3806680A JP S56134826 A JPS56134826 A JP S56134826A
- Authority
- JP
- Japan
- Prior art keywords
- envelope
- positive
- negative
- circuits
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
PURPOSE:To convert the analogue signal to a binary surely independently of the amplitude of the input waveform, by using the potential of the positive envelope waveform as the steady state potential of the negative envelope circuit and by using the potential of the negative envelope waveform as the steady state potential of the positive envelope circuit and by forming envelope waveforms on the basis of potentials of positive and negative waveforms opposite to each other. CONSTITUTION:Analogue signal (a) is amplified by amplifying circuit 1 and is inputted to envelope circuits 2A and 2B and comparator 4. Positive and negative steady state potential circuits 5A and 5B are provided in succeeding stages of envelope circuits 2A and 2B respectively, and outputs of steady state potential circuits are inputted to positive and negative envelope circuits in opposite sides of each other, and envelope waveforms are formed on the basis of outputs of steady state potential circuits in opposite sides of each other and are outputted to slice level generating circuit 3. Slice level generating circuit 3 detects middle points of positive and negative envelopes and inputs them to comparator circuit 4 as slice levels, and analogue signal (a) is compared with these slice levels by circuit 4, and digital output (b) is outputted.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3806680A JPS56134826A (en) | 1980-03-25 | 1980-03-25 | Binary circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3806680A JPS56134826A (en) | 1980-03-25 | 1980-03-25 | Binary circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56134826A true JPS56134826A (en) | 1981-10-21 |
Family
ID=12515112
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP3806680A Pending JPS56134826A (en) | 1980-03-25 | 1980-03-25 | Binary circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56134826A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5133393A (en) * | 1974-09-13 | 1976-03-22 | Canon Kk |
-
1980
- 1980-03-25 JP JP3806680A patent/JPS56134826A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5133393A (en) * | 1974-09-13 | 1976-03-22 | Canon Kk |
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