JPS56127259A - Information processor - Google Patents

Information processor

Info

Publication number
JPS56127259A
JPS56127259A JP3053080A JP3053080A JPS56127259A JP S56127259 A JPS56127259 A JP S56127259A JP 3053080 A JP3053080 A JP 3053080A JP 3053080 A JP3053080 A JP 3053080A JP S56127259 A JPS56127259 A JP S56127259A
Authority
JP
Japan
Prior art keywords
memory
unit
controller
decoder
receives
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3053080A
Other languages
Japanese (ja)
Inventor
Tsuneo Kinoshita
Fumitaka Sato
Isamu Yamazaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP3053080A priority Critical patent/JPS56127259A/en
Publication of JPS56127259A publication Critical patent/JPS56127259A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
    • G06F12/0646—Configuration or reconfiguration
    • G06F12/0653—Configuration or reconfiguration with centralised address assignment

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To realize an exchange of various kinds of information between an operation controller and an external device with an allotment of a small number of pins, by connecting only the memory unit that receives the selection signal from a decoder to the operation controller via the common memory address line and the memory data line. CONSTITUTION:The unit address register 103 delivers the unit address from the operation controller 100 for selection of a memory unit. On the other hand, the decoder 300 receives the unit addresses delivered from the common memory address line MAL, the memory data line MDL provided between the controller 100 and plural types of memory units plus the controller 100, and obtains the memory unit selection signal that is proper to a memory unit following the code. Then only the memory unit that receives the selection signal from the decoder 300 performs an exchange of information to the controller 100 via the common memory address line and the memory data line.
JP3053080A 1980-03-11 1980-03-11 Information processor Pending JPS56127259A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3053080A JPS56127259A (en) 1980-03-11 1980-03-11 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3053080A JPS56127259A (en) 1980-03-11 1980-03-11 Information processor

Publications (1)

Publication Number Publication Date
JPS56127259A true JPS56127259A (en) 1981-10-05

Family

ID=12306347

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3053080A Pending JPS56127259A (en) 1980-03-11 1980-03-11 Information processor

Country Status (1)

Country Link
JP (1) JPS56127259A (en)

Similar Documents

Publication Publication Date Title
DE3175054D1 (en) Modular data processing system
JPS6436336A (en) Calculator system
JPS57105879A (en) Control system for storage device
ES8406758A1 (en) Operating system supervisor.
ES8303746A1 (en) Request queueing in memory controller.
DE3887552D1 (en) Time control for double connection.
DE69327504T2 (en) Data processor with operational units that share groups of register memories
JPS56127259A (en) Information processor
FR2258668A1 (en) Data processor tracing unit - permits real time monitoring of system operation especially in telephone exchange systems
EP0111161A3 (en) Device for initiating microinstructions for at least two independently working function units in an integrated microprogrammed electronic module, and method for its operation
FR2438298B1 (en) CONTROL MEMORY OF A DATA PROCESSING SYSTEM
JPS5334429A (en) Memory control system
JPS5326632A (en) Common memory control unit
JPS54124902A (en) Data transmission-reception system
JPS5725045A (en) Data processing equipment
JPS5730060A (en) Address space expansion system
JPS5764835A (en) Direct memory access system of microprocessor
JPS56118133A (en) Direct memory access circuit
JPS6415853A (en) Memory access processing system
JPS56153421A (en) Information processor
JPS57168364A (en) Multi-processor system
JPS5750378A (en) Control system of data processor
JPS56114026A (en) Data processor
JPS51144137A (en) Input/output data control unit
JPS53116010A (en) Terminal control system