JPS56124959A - Check system of digital equipment - Google Patents
Check system of digital equipmentInfo
- Publication number
- JPS56124959A JPS56124959A JP2666180A JP2666180A JPS56124959A JP S56124959 A JPS56124959 A JP S56124959A JP 2666180 A JP2666180 A JP 2666180A JP 2666180 A JP2666180 A JP 2666180A JP S56124959 A JPS56124959 A JP S56124959A
- Authority
- JP
- Japan
- Prior art keywords
- program
- timer
- hard
- equipment
- abnormal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
Abstract
PURPOSE:To check each memory practically, by installing a program processing time supervisory timer to the outside of the digital equipment as hardware, and setting or resetting the hard-timer in accordance with start and end of a program. CONSTITUTION:A hard-timer is connected to the outside of the digital equipment 1 equipped with an operational processing equipment, a program store memory and a data store memory, through the address bus, the data bus and the bus for outputting a control signal. On this hard-timer are provided a timing generating circuit 2, a time-over detection counter 3, a time-short detection counter 4, and an abnormal store control circuit 5. And, the counter 3 and 4 are set or reset whenever execution of a program is started and ended, the function and operation of the equipment 1 are checked prior to execution of a program, and when they are abnormal, an abnormal alarm signal is generated.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2666180A JPS56124959A (en) | 1980-03-05 | 1980-03-05 | Check system of digital equipment |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2666180A JPS56124959A (en) | 1980-03-05 | 1980-03-05 | Check system of digital equipment |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56124959A true JPS56124959A (en) | 1981-09-30 |
Family
ID=12199595
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2666180A Pending JPS56124959A (en) | 1980-03-05 | 1980-03-05 | Check system of digital equipment |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56124959A (en) |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5420636A (en) * | 1977-07-15 | 1979-02-16 | Mitsubishi Electric Corp | Computer |
-
1980
- 1980-03-05 JP JP2666180A patent/JPS56124959A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5420636A (en) * | 1977-07-15 | 1979-02-16 | Mitsubishi Electric Corp | Computer |
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