JPS56122550A - Data switching system for time division circuit - Google Patents
Data switching system for time division circuitInfo
- Publication number
- JPS56122550A JPS56122550A JP2691380A JP2691380A JPS56122550A JP S56122550 A JPS56122550 A JP S56122550A JP 2691380 A JP2691380 A JP 2691380A JP 2691380 A JP2691380 A JP 2691380A JP S56122550 A JPS56122550 A JP S56122550A
- Authority
- JP
- Japan
- Prior art keywords
- data
- time division
- dcec
- multiplicity
- receiving data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/50—Circuit switching systems, i.e. systems in which the path is physically permanent during the communication
- H04L12/52—Circuit switching systems, i.e. systems in which the path is physically permanent during the communication using time division techniques
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Data Exchanges In Wide-Area Networks (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
Abstract
PURPOSE:To make it possible to use all the equipments, and to entirely make the best of the functions of the switchboard body, by executing the multiplicity and distribution of the transmission/receiving data by use of the accomodating position information of each equipment in the office circuit terminating equipment group. CONSTITUTION:A transmission data and a receiving data are transferred at plural bits each by means of time division multiplicity between the plural office circuit terminating equipment DCEC groups which constitute channels, and the buffer memories SDB, RDB which have been placed so as to correspond to said DCEC groups, respectively. Also, the multiplicity and/or distribution of the transmission data and the receiving data are executed in accordance with the information showing the accomodating position in the DCEC group, which is read out by synchronizing with the time division multiple data from the circuit control memory LCM placed so as to correspond to the buffer memory. Furthermore, a data between the buffer memories is transferred in accordance with the connecting information which the switchboard has as calling correspondence.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2691380A JPS56122550A (en) | 1980-03-03 | 1980-03-03 | Data switching system for time division circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2691380A JPS56122550A (en) | 1980-03-03 | 1980-03-03 | Data switching system for time division circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56122550A true JPS56122550A (en) | 1981-09-26 |
JPS6144427B2 JPS6144427B2 (en) | 1986-10-02 |
Family
ID=12206447
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2691380A Granted JPS56122550A (en) | 1980-03-03 | 1980-03-03 | Data switching system for time division circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56122550A (en) |
-
1980
- 1980-03-03 JP JP2691380A patent/JPS56122550A/en active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS6144427B2 (en) | 1986-10-02 |
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