JPS56121156A - Hang detection system of data processing equipment - Google Patents

Hang detection system of data processing equipment

Info

Publication number
JPS56121156A
JPS56121156A JP2314180A JP2314180A JPS56121156A JP S56121156 A JPS56121156 A JP S56121156A JP 2314180 A JP2314180 A JP 2314180A JP 2314180 A JP2314180 A JP 2314180A JP S56121156 A JPS56121156 A JP S56121156A
Authority
JP
Japan
Prior art keywords
cpu1
processing equipment
signal
interruption
hang
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2314180A
Other languages
Japanese (ja)
Other versions
JPS6030979B2 (en
Inventor
Hidekiyo Ozawa
Yuji Oinaga
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55023141A priority Critical patent/JPS6030979B2/en
Publication of JPS56121156A publication Critical patent/JPS56121156A/en
Publication of JPS6030979B2 publication Critical patent/JPS6030979B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE:To prevent a system-down by installing two processing equipments, and making the second processing equipment forcibly generate a machine check interruption, in case the first processing equipment has got into a hang state. CONSTITUTION:When a hang occurs in the CPU1, an end signal IEND does not come to the processing equipment 2 from the CPU1. As a result, the timer 23 generates a signal after a prescribed time has elapsed, and in that case, when the CPU1 is not a stop state, a wait state nor a check stop state, a signal for stopping the clock is provided to the clock control circuit 24. At the same time, the signal is provided to the control circuit 25, as well, and the contents in the CPU are saved into the memory 26 under control of the circuit 25. After that, the internal status information which has been saved in the memory 26 is returned to the machine check logout are of the CPU1, an interruption code is set to the interruption register 12, and after that, the CPU1 is started.
JP55023141A 1980-02-26 1980-02-26 Hang detection method for data processing equipment Expired JPS6030979B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55023141A JPS6030979B2 (en) 1980-02-26 1980-02-26 Hang detection method for data processing equipment

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55023141A JPS6030979B2 (en) 1980-02-26 1980-02-26 Hang detection method for data processing equipment

Publications (2)

Publication Number Publication Date
JPS56121156A true JPS56121156A (en) 1981-09-22
JPS6030979B2 JPS6030979B2 (en) 1985-07-19

Family

ID=12102275

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55023141A Expired JPS6030979B2 (en) 1980-02-26 1980-02-26 Hang detection method for data processing equipment

Country Status (1)

Country Link
JP (1) JPS6030979B2 (en)

Also Published As

Publication number Publication date
JPS6030979B2 (en) 1985-07-19

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