JPS5611535A - Data input and output control system - Google Patents

Data input and output control system

Info

Publication number
JPS5611535A
JPS5611535A JP8729979A JP8729979A JPS5611535A JP S5611535 A JPS5611535 A JP S5611535A JP 8729979 A JP8729979 A JP 8729979A JP 8729979 A JP8729979 A JP 8729979A JP S5611535 A JPS5611535 A JP S5611535A
Authority
JP
Japan
Prior art keywords
unit
data transfer
data input
buffer circuit
control system
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8729979A
Other languages
Japanese (ja)
Inventor
Hirotaka Kimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP8729979A priority Critical patent/JPS5611535A/en
Publication of JPS5611535A publication Critical patent/JPS5611535A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To enable the data transfer between the main memory unit and the data input and output unit in high speed and high efficiency, by providing the flag control circuit and the read buffer circuit at the channel control unit. CONSTITUTION:The channel control unit 2 is provided with the flag control circuit 14, read buffer circuit 12, write buffer circuit 13 and address buffer circuit 11. Thus, the data transfer between the main memory unit 1 and the unit 2 is made with the data transfer unit of the unit 1, and the data transfer between the data input and output unit 3 and the unit 2 is made the data transfer unit of te unit 3. Thus, the read-out cycle and the write-in cycle can be quickened, allowing to make the data transfer between the units 1 and 2 in high speed and high efficiency.
JP8729979A 1979-07-10 1979-07-10 Data input and output control system Pending JPS5611535A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8729979A JPS5611535A (en) 1979-07-10 1979-07-10 Data input and output control system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8729979A JPS5611535A (en) 1979-07-10 1979-07-10 Data input and output control system

Publications (1)

Publication Number Publication Date
JPS5611535A true JPS5611535A (en) 1981-02-04

Family

ID=13910938

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8729979A Pending JPS5611535A (en) 1979-07-10 1979-07-10 Data input and output control system

Country Status (1)

Country Link
JP (1) JPS5611535A (en)

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