JPS56114022A - Clock control system for electronic computer - Google Patents
Clock control system for electronic computerInfo
- Publication number
- JPS56114022A JPS56114022A JP1691880A JP1691880A JPS56114022A JP S56114022 A JPS56114022 A JP S56114022A JP 1691880 A JP1691880 A JP 1691880A JP 1691880 A JP1691880 A JP 1691880A JP S56114022 A JPS56114022 A JP S56114022A
- Authority
- JP
- Japan
- Prior art keywords
- clock
- microinstruction
- cycle
- control
- signals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/22—Microcontrol or microprogram arrangements
- G06F9/223—Execution means for microinstructions irrespective of the microinstruction function, e.g. decoding of microinstructions and nanoinstructions; timing of microinstructions; programmable logic arrays; delays and fan-out problems
Abstract
PURPOSE:To ensure an execution of an arithmetic action for a microinstruction in the minimum time, by providing the clock control bit to the microinstruction and controlling the cycle of the clock. CONSTITUTION:The clock control bit is provided to the microinstruction read out of a micromemory and decoded into two control signals B1 and B2. These two control signals are applied to an FF circuit that divides the basic clock 1 and delivers the control clock. In this case, the clock 2 is obtained with the cycle double as much as the clock 1 when both signals B1 and B2 are 0, with a triple cycle when the signals B1 and B2 are 1 and 0, respectively, and with a quadruple cycle when the signal B2 is 1, respectively. Accordingly, the arithmetic process can be executed in the minimum time for a microinstruction by setting previously the operation time corresponding to each microinstruction in the control field.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1691880A JPS56114022A (en) | 1980-02-14 | 1980-02-14 | Clock control system for electronic computer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1691880A JPS56114022A (en) | 1980-02-14 | 1980-02-14 | Clock control system for electronic computer |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56114022A true JPS56114022A (en) | 1981-09-08 |
Family
ID=11929504
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1691880A Pending JPS56114022A (en) | 1980-02-14 | 1980-02-14 | Clock control system for electronic computer |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56114022A (en) |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4979142A (en) * | 1972-12-01 | 1974-07-31 | ||
JPS51147142A (en) * | 1975-06-13 | 1976-12-17 | Hitachi Ltd | Control system of machine cycle of micro instruction |
JPS52116035A (en) * | 1976-03-26 | 1977-09-29 | Hitachi Ltd | Data processing unit |
-
1980
- 1980-02-14 JP JP1691880A patent/JPS56114022A/en active Pending
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS4979142A (en) * | 1972-12-01 | 1974-07-31 | ||
JPS51147142A (en) * | 1975-06-13 | 1976-12-17 | Hitachi Ltd | Control system of machine cycle of micro instruction |
JPS52116035A (en) * | 1976-03-26 | 1977-09-29 | Hitachi Ltd | Data processing unit |
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