JPS56111111A - Automatic recording level setter - Google Patents
Automatic recording level setterInfo
- Publication number
- JPS56111111A JPS56111111A JP1415280A JP1415280A JPS56111111A JP S56111111 A JPS56111111 A JP S56111111A JP 1415280 A JP1415280 A JP 1415280A JP 1415280 A JP1415280 A JP 1415280A JP S56111111 A JPS56111111 A JP S56111111A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- level
- recording
- switch
- automatic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B5/00—Recording by magnetisation or demagnetisation of a record carrier; Reproducing by magnetic means; Record carriers therefor
- G11B5/02—Recording, reproducing, or erasing methods; Read, write or erase circuits therefor
- G11B5/027—Analogue recording
Landscapes
- Signal Processing Not Specific To The Method Of Recording And Reproducing (AREA)
- Control Of Amplification And Gain Control (AREA)
Abstract
PURPOSE:To enable to obtain excellent recording even for automatic answering recording, by detecting input signals through a filter circuit, comparing the level with the set level, adjusting the gain control circuit with the maximum input level and operating this circuit via a delay circuit. CONSTITUTION:When an automatic set switch 7 is depressed, a time set circuit 6 is driven and the pulse with predetermined time width is fed to a maximum value storage circuit 5. On the other hand, the signal given to an input terminal 1 is made for amplitude correction according to the frequency with a filter circuit 40, then it is detected at a level detector 4, and the gain of a gain control circuit 3 is controlled with the signal of maximum level in the set time at the maximum value storage circuit 5. The output 2 is output to a recording head 34 via a recording amplifier 33. When a power switch (or timer switch) is on, an automatic recording level set circuit A is operated via a power supply circuit 35, differentiation circuit 36, delay circuit 41, switching element 38 and switch 37, enabling excellent recording even for automatic answering recording.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1415280A JPS56111111A (en) | 1980-02-06 | 1980-02-06 | Automatic recording level setter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1415280A JPS56111111A (en) | 1980-02-06 | 1980-02-06 | Automatic recording level setter |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56111111A true JPS56111111A (en) | 1981-09-02 |
JPS6245621B2 JPS6245621B2 (en) | 1987-09-28 |
Family
ID=11853171
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1415280A Granted JPS56111111A (en) | 1980-02-06 | 1980-02-06 | Automatic recording level setter |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56111111A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6126901A (en) * | 1984-07-18 | 1986-02-06 | Pioneer Electronic Corp | Reproduced sound recording control system |
-
1980
- 1980-02-06 JP JP1415280A patent/JPS56111111A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6126901A (en) * | 1984-07-18 | 1986-02-06 | Pioneer Electronic Corp | Reproduced sound recording control system |
Also Published As
Publication number | Publication date |
---|---|
JPS6245621B2 (en) | 1987-09-28 |
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