JPS5610946A - Manufacture of resin sealeded type semiconductor device - Google Patents

Manufacture of resin sealeded type semiconductor device

Info

Publication number
JPS5610946A
JPS5610946A JP8626679A JP8626679A JPS5610946A JP S5610946 A JPS5610946 A JP S5610946A JP 8626679 A JP8626679 A JP 8626679A JP 8626679 A JP8626679 A JP 8626679A JP S5610946 A JPS5610946 A JP S5610946A
Authority
JP
Japan
Prior art keywords
resin
mold
lead wire
wire group
burr
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8626679A
Other languages
Japanese (ja)
Inventor
Yutaka Morita
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP8626679A priority Critical patent/JPS5610946A/en
Publication of JPS5610946A publication Critical patent/JPS5610946A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To void occurrence of burr in a resin sealed type semiconductor device by winding a buffer made of resin at the position external of a mold of lead wire group coupled as prescribed and fixed with a semiconductor element at the ends when inserting the ends of the lead wire group at the element side into the space of the mold to seal it with the resin. CONSTITUTION:A semiconductor element 2 is fixed to one end of a plurality of lead wire group 1, and electrodes of the element 2 are connected through fine metallic wires 3 to the ends of other lead wires. Then, the ends of the lead wire group 1 of the element 2 to be fixed to the element 2 are inserted into the space 5 of a mold having upper and lower molds 6 and 7, resin 9 is filled in the space 5 to form resin seal 4 at the end of the lead wire group 1. Buffers 15 made of epoxy resin or the like are wound at the portions disposed externally of the mold of the lead wire group 1 while contacting them with the side surface of the mold. In this manner, it can eliminate the tolerance of the gap occurred when forming the mold so as to eliminate the production of burr at the seal 4 and to thus remove the necessity of removing the burr thereat.
JP8626679A 1979-07-06 1979-07-06 Manufacture of resin sealeded type semiconductor device Pending JPS5610946A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8626679A JPS5610946A (en) 1979-07-06 1979-07-06 Manufacture of resin sealeded type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8626679A JPS5610946A (en) 1979-07-06 1979-07-06 Manufacture of resin sealeded type semiconductor device

Publications (1)

Publication Number Publication Date
JPS5610946A true JPS5610946A (en) 1981-02-03

Family

ID=13882009

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8626679A Pending JPS5610946A (en) 1979-07-06 1979-07-06 Manufacture of resin sealeded type semiconductor device

Country Status (1)

Country Link
JP (1) JPS5610946A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0637081A3 (en) * 1993-07-27 1996-03-20 Siemens Ag Micro sensor with plug connections.
CN107086183A (en) * 2016-02-16 2017-08-22 富士电机株式会社 The manufacture method and semiconductor module of semiconductor module

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0637081A3 (en) * 1993-07-27 1996-03-20 Siemens Ag Micro sensor with plug connections.
CN107086183A (en) * 2016-02-16 2017-08-22 富士电机株式会社 The manufacture method and semiconductor module of semiconductor module
JP2017147295A (en) * 2016-02-16 2017-08-24 富士電機株式会社 Method of manufacturing semiconductor module and semiconductor module
CN107086183B (en) * 2016-02-16 2021-12-28 富士电机株式会社 Method for manufacturing semiconductor module and semiconductor module

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