JPS55148446A - Component for electric circuit - Google Patents

Component for electric circuit

Info

Publication number
JPS55148446A
JPS55148446A JP5725479A JP5725479A JPS55148446A JP S55148446 A JPS55148446 A JP S55148446A JP 5725479 A JP5725479 A JP 5725479A JP 5725479 A JP5725479 A JP 5725479A JP S55148446 A JPS55148446 A JP S55148446A
Authority
JP
Japan
Prior art keywords
projection
resin
wall
case
filled
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5725479A
Other languages
Japanese (ja)
Inventor
Fumiyoshi Matsumura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP5725479A priority Critical patent/JPS55148446A/en
Publication of JPS55148446A publication Critical patent/JPS55148446A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Casings For Electric Apparatus (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To obtain a semiconductor element having a high sealability by forming an annular projection being lower than an outer wall and higher than a circuit element to be sealed on the inner surface of a case, installing the circuit element within the projection and filling resin inside the projection. CONSTITUTION:An annular projection 15 is formed in a metal or resin case 11. The projection 15 is formed lower than the height of the outer wall 16 of the case 11 and higher than a hybrid integrated circuit 17 implanted with an external lead wire 18 mounted insie the wall 16. After the hybrid integrated circuit 17 is mounted within the projection 15, soft silicone resin 12 is filled therein, and hard epoxy resin 13 is filled thereon. Since the soft resin 12 is limited to the inside of the projection 15, the contact area between the resin 13 and the outer wall 16 of the case 11 becomes wide enough so as to strengthen the adhering force therebetween.
JP5725479A 1979-05-10 1979-05-10 Component for electric circuit Pending JPS55148446A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5725479A JPS55148446A (en) 1979-05-10 1979-05-10 Component for electric circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5725479A JPS55148446A (en) 1979-05-10 1979-05-10 Component for electric circuit

Publications (1)

Publication Number Publication Date
JPS55148446A true JPS55148446A (en) 1980-11-19

Family

ID=13050384

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5725479A Pending JPS55148446A (en) 1979-05-10 1979-05-10 Component for electric circuit

Country Status (1)

Country Link
JP (1) JPS55148446A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0114474A1 (en) * 1982-12-27 1984-08-01 Western Electric Company, Incorporated Methods of encapsulating electronic circuits

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0114474A1 (en) * 1982-12-27 1984-08-01 Western Electric Company, Incorporated Methods of encapsulating electronic circuits

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