JPS56107663A - Data sending control system - Google Patents
Data sending control systemInfo
- Publication number
- JPS56107663A JPS56107663A JP1030180A JP1030180A JPS56107663A JP S56107663 A JPS56107663 A JP S56107663A JP 1030180 A JP1030180 A JP 1030180A JP 1030180 A JP1030180 A JP 1030180A JP S56107663 A JPS56107663 A JP S56107663A
- Authority
- JP
- Japan
- Prior art keywords
- buffer
- sending
- vacant
- send
- processing part
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
- G06F13/4226—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with asynchronous protocol
Abstract
PURPOSE:To enable to operate a data request signal and a sending end signal with the same signal, by constituting the system so that the request signal is not output even if the send-out queuing buffer is vacant, in case the display information exists, and after that, the request signal is output when the circuit sending-out buffer has been vacant. CONSTITUTION:In case a character to be sent out from the processing part 11 is gone, it is transferred to the buffer with the final character display, also the character is sent out to the circuit, and even if the send-out queuing buffer 12 becomes vacant, ready for sending is not informed but it is informed after both the buffer 12 and the circuit sending-out buffer 13 have become vacant. As a result, 2 reports informing that the sending-out buffer has been vacant (REQ1) and the transmission has been completed (REQ2) become 1 ready for sending (REQ) report, the processing part 11 is able to easily control to send out a data, and the processing capacity of the processing part can be elevated without increasing the interface line.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1030180A JPS56107663A (en) | 1980-01-31 | 1980-01-31 | Data sending control system |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1030180A JPS56107663A (en) | 1980-01-31 | 1980-01-31 | Data sending control system |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS56107663A true JPS56107663A (en) | 1981-08-26 |
Family
ID=11746428
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1030180A Pending JPS56107663A (en) | 1980-01-31 | 1980-01-31 | Data sending control system |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56107663A (en) |
-
1980
- 1980-01-31 JP JP1030180A patent/JPS56107663A/en active Pending
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