JPS56105311A - Pcm recording and reproducing device - Google Patents
Pcm recording and reproducing deviceInfo
- Publication number
- JPS56105311A JPS56105311A JP782980A JP782980A JPS56105311A JP S56105311 A JPS56105311 A JP S56105311A JP 782980 A JP782980 A JP 782980A JP 782980 A JP782980 A JP 782980A JP S56105311 A JPS56105311 A JP S56105311A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- subtractor
- sample values
- output
- level difference
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
- H03M1/08—Continuously compensating for, or preventing, undesired influence of physical parameters of noise
- H03M1/0863—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of switching transients, e.g. glitches
- H03M1/0881—Continuously compensating for, or preventing, undesired influence of physical parameters of noise of switching transients, e.g. glitches by forcing a gradual change from one output level to the next, e.g. soft-start
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
- H03M1/66—Digital/analogue converters
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Signal Processing For Digital Recording And Reproducing (AREA)
- Analogue/Digital Conversion (AREA)
Abstract
PURPOSE:To improve the ratio of quantizing noise to signals at the reproducing time without increment of the sampling frequency and the number of quantization bits, by subjecting the level difference between adjacent sample values to the insertion processing digitally. CONSTITUTION:Two digital data V0 and V1 which are taken out synchronously with the sampling period according to time elapse are written in storage device 1 and are read to obtain the absolute value of the difference between data V0 and V1 by subtractor 2, and the 1/n value is obtained by divider 3, and it is added cumulatively in 4 by the clock signal of the frequency (n) times as high as the data rate. The addition signal is given to operating circuit 6 and is added to or subtracted from signal V0 from device 1. This addition or subtraction is determined dependently upon the quantitative relation between V0 and V1 and corresponds as the output of subtractor 2. A staircase wave signal is obtained as the output of circuit 6, and the level difference between two sample values is filled up with a pile of finer steps.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP782980A JPS56105311A (en) | 1980-01-28 | 1980-01-28 | Pcm recording and reproducing device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP782980A JPS56105311A (en) | 1980-01-28 | 1980-01-28 | Pcm recording and reproducing device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS56105311A true JPS56105311A (en) | 1981-08-21 |
JPS6329346B2 JPS6329346B2 (en) | 1988-06-13 |
Family
ID=11676479
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP782980A Granted JPS56105311A (en) | 1980-01-28 | 1980-01-28 | Pcm recording and reproducing device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS56105311A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61184993A (en) * | 1985-02-13 | 1986-08-18 | Sony Corp | Correcting device for speed error |
JPH01177617U (en) * | 1988-06-03 | 1989-12-19 | ||
JPH0360526A (en) * | 1989-07-28 | 1991-03-15 | Yokogawa Electric Corp | D/a converting circuit |
JP2019106701A (en) * | 2017-12-14 | 2019-06-27 | スティヒティング・イメック・ネーデルラントStichting IMEC Nederland | Digital power amplifier circuit |
JP2021101499A (en) * | 2019-12-24 | 2021-07-08 | 日本電波工業株式会社 | Data output circuit |
-
1980
- 1980-01-28 JP JP782980A patent/JPS56105311A/en active Granted
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS61184993A (en) * | 1985-02-13 | 1986-08-18 | Sony Corp | Correcting device for speed error |
JPH01177617U (en) * | 1988-06-03 | 1989-12-19 | ||
JPH0360526A (en) * | 1989-07-28 | 1991-03-15 | Yokogawa Electric Corp | D/a converting circuit |
JP2019106701A (en) * | 2017-12-14 | 2019-06-27 | スティヒティング・イメック・ネーデルラントStichting IMEC Nederland | Digital power amplifier circuit |
JP2021101499A (en) * | 2019-12-24 | 2021-07-08 | 日本電波工業株式会社 | Data output circuit |
Also Published As
Publication number | Publication date |
---|---|
JPS6329346B2 (en) | 1988-06-13 |
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