JPS56100411A - Manufacture of semiconductor element - Google Patents

Manufacture of semiconductor element

Info

Publication number
JPS56100411A
JPS56100411A JP216480A JP216480A JPS56100411A JP S56100411 A JPS56100411 A JP S56100411A JP 216480 A JP216480 A JP 216480A JP 216480 A JP216480 A JP 216480A JP S56100411 A JPS56100411 A JP S56100411A
Authority
JP
Japan
Prior art keywords
layer
substrate
diffusion
oxidization
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP216480A
Other languages
Japanese (ja)
Inventor
Fumio Tobioka
Yukinori Koba
Shoichi Kitane
Kenji Azetsubo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP216480A priority Critical patent/JPS56100411A/en
Publication of JPS56100411A publication Critical patent/JPS56100411A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/223Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a gaseous phase

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Weting (AREA)

Abstract

PURPOSE:To obtain the semiconductor device having stable properties by providing a P layer selectively on the N<+> layer of an N type substrate, making the surface of substrates face with each other and subjecting the same to stack diffusion with oxidization. CONSTITUTION:The N<+> layer 2 is left on one surface of the N type Si substrate 11 and the P layer 13 is provided on the substrate 11. By using a resist mask 14, the P layer 13 is removed through etching by the mixed liquid of fluoric acid, nitric acid and acetic acid and then the mask is removed. Next, by wet oxidization, the front and back surfaces of the substrate is covered with an SiO2 film 15. Then, the front surfaces and back surfaces of the substrates 11 are made opposed to each other respectively and are set to a jig 19. A central hole 18 helps gas to permeate. After that, the substrate is processed at high temperature in the ambience of N2: O2=10:90 and the surface thereof is subjected to the stack diffusion with oxidization, whereby abnormal diffusion of impurites is prevented. After the diffusion, the SiO2 film is removed by HF liquid and an SiO2 protection film is attached, whereby an emitter layer is formed. By this constitution, the NPN element with little unevenness of a base layer and stable properties is obtained.
JP216480A 1980-01-14 1980-01-14 Manufacture of semiconductor element Pending JPS56100411A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP216480A JPS56100411A (en) 1980-01-14 1980-01-14 Manufacture of semiconductor element

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP216480A JPS56100411A (en) 1980-01-14 1980-01-14 Manufacture of semiconductor element

Publications (1)

Publication Number Publication Date
JPS56100411A true JPS56100411A (en) 1981-08-12

Family

ID=11521713

Family Applications (1)

Application Number Title Priority Date Filing Date
JP216480A Pending JPS56100411A (en) 1980-01-14 1980-01-14 Manufacture of semiconductor element

Country Status (1)

Country Link
JP (1) JPS56100411A (en)

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