JPS56100367A - Programmable logic array device - Google Patents

Programmable logic array device

Info

Publication number
JPS56100367A
JPS56100367A JP247180A JP247180A JPS56100367A JP S56100367 A JPS56100367 A JP S56100367A JP 247180 A JP247180 A JP 247180A JP 247180 A JP247180 A JP 247180A JP S56100367 A JPS56100367 A JP S56100367A
Authority
JP
Japan
Prior art keywords
bits
tested
output
bit
readout
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP247180A
Other languages
Japanese (ja)
Inventor
Hiroto Sato
Yoshio Komoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Takeda Riken Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advantest Corp, Takeda Riken Industries Co Ltd filed Critical Advantest Corp
Priority to JP247180A priority Critical patent/JPS56100367A/en
Publication of JPS56100367A publication Critical patent/JPS56100367A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318516—Test of programmable logic devices [PLDs]

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE:To enable data processing of many bits with a bus line of less number of bits, by obtaining one pattern signal through a plurality of times of readout outputs from an input and output pattern memory device and using the data bus line in time sharing manner. CONSTITUTION:When the output of a body to be tested 1 is 8-16-bit, a storage device of 8-bit output is used for an output pattern storage device 17. That is, in testing an object to be tested with less number of bits, the output pattern in 8-bit is read out with one readout. When the object to be tested with many number of bits of output is read out, the output pattern in 16-bit is read out with the readout of two times. Registers 20a, 20b have respectively the capacity of 8-bit, and when the object to be tested of less number of bits is tested, the readout output of a storage device 17 is contained only in a register 20a, and when the object to be tested for many number of bits is tested, the output is alternately stored in 20a and 20b, and data are processed via a data bus line D. With this constitution, the data processing in many number of bits is made with the bus line of less number of bits.
JP247180A 1980-01-11 1980-01-11 Programmable logic array device Pending JPS56100367A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP247180A JPS56100367A (en) 1980-01-11 1980-01-11 Programmable logic array device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP247180A JPS56100367A (en) 1980-01-11 1980-01-11 Programmable logic array device

Publications (1)

Publication Number Publication Date
JPS56100367A true JPS56100367A (en) 1981-08-12

Family

ID=11530225

Family Applications (1)

Application Number Title Priority Date Filing Date
JP247180A Pending JPS56100367A (en) 1980-01-11 1980-01-11 Programmable logic array device

Country Status (1)

Country Link
JP (1) JPS56100367A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5133700A (en) * 1974-09-17 1976-03-22 Tokyo Shibaura Electric Co SHOKUHIN JIDOHAN BAIKI
JPS5478047A (en) * 1977-12-02 1979-06-21 Takeda Riken Ind Co Ltd Programmable logic array tester

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5133700A (en) * 1974-09-17 1976-03-22 Tokyo Shibaura Electric Co SHOKUHIN JIDOHAN BAIKI
JPS5478047A (en) * 1977-12-02 1979-06-21 Takeda Riken Ind Co Ltd Programmable logic array tester

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