JPS5599858A - Signal processing circuit - Google Patents

Signal processing circuit

Info

Publication number
JPS5599858A
JPS5599858A JP688679A JP688679A JPS5599858A JP S5599858 A JPS5599858 A JP S5599858A JP 688679 A JP688679 A JP 688679A JP 688679 A JP688679 A JP 688679A JP S5599858 A JPS5599858 A JP S5599858A
Authority
JP
Japan
Prior art keywords
output
amplifier
circuit
signal
control
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP688679A
Other languages
Japanese (ja)
Other versions
JPS6056354B2 (en
Inventor
Nobukazu Hosoya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP54006886A priority Critical patent/JPS6056354B2/en
Publication of JPS5599858A publication Critical patent/JPS5599858A/en
Publication of JPS6056354B2 publication Critical patent/JPS6056354B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H20/00—Arrangements for broadcast or for distribution combined with broadcast
    • H04H20/86—Arrangements characterised by the broadcast information itself
    • H04H20/88—Stereophonic broadcast systems
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H04B1/1646—Circuits adapted for the reception of stereophonic signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04H—BROADCAST COMMUNICATION
    • H04H40/00—Arrangements specially adapted for receiving broadcast information
    • H04H40/18—Arrangements characterised by circuits or components specially adapted for receiving
    • H04H40/27—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95
    • H04H40/36—Arrangements characterised by circuits or components specially adapted for receiving specially adapted for broadcast systems covered by groups H04H20/53 - H04H20/95 specially adapted for stereophonic broadcast receiving

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Stereo-Broadcasting Methods (AREA)
  • Television Receiver Circuits (AREA)

Abstract

PURPOSE:To avoid the generation of pop sound, by producing the output in response to the instruction, controlling the operation of each differential amplifier according to each instruction made, and avoiding the variation in DC level at the input terminal of the output circuit in the selection control of each mode. CONSTITUTION:The first and second differential amplifiers A1, A2 respectively inputting the first signal from the first input terminal 28, differential amplifiers A3, A4 respectively inputting the second signal from the second input termianl 29, and the fifth differential amplifier A5 at the upper stage of A3, are provided. Further, the first output circuit 30 introducing the output signal of the amplifier A2 and/or A3, and the second output circuit 31 introducing the output of the amplifier A1 and/or A4 are provided. The operation of the amplifiers A1-A4 is individually controlled with the control signal from the first control circuit 21, the operaion of the amplifier A5 and the circuit 21 is controlled with the second control circuit 22, allowing to avoid the DC level of each input termianl of the output circuits 30, 31 from being fluctuated independently of the control mode of the circuits 21, 22.
JP54006886A 1979-01-23 1979-01-23 signal processing circuit Expired JPS6056354B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54006886A JPS6056354B2 (en) 1979-01-23 1979-01-23 signal processing circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54006886A JPS6056354B2 (en) 1979-01-23 1979-01-23 signal processing circuit

Publications (2)

Publication Number Publication Date
JPS5599858A true JPS5599858A (en) 1980-07-30
JPS6056354B2 JPS6056354B2 (en) 1985-12-10

Family

ID=11650706

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54006886A Expired JPS6056354B2 (en) 1979-01-23 1979-01-23 signal processing circuit

Country Status (1)

Country Link
JP (1) JPS6056354B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5838165A (en) * 1981-09-01 1983-03-05 Mitsubishi Electric Corp Recorder

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5838165A (en) * 1981-09-01 1983-03-05 Mitsubishi Electric Corp Recorder

Also Published As

Publication number Publication date
JPS6056354B2 (en) 1985-12-10

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