JPS5597629A - Programmable control unit - Google Patents

Programmable control unit

Info

Publication number
JPS5597629A
JPS5597629A JP584279A JP584279A JPS5597629A JP S5597629 A JPS5597629 A JP S5597629A JP 584279 A JP584279 A JP 584279A JP 584279 A JP584279 A JP 584279A JP S5597629 A JPS5597629 A JP S5597629A
Authority
JP
Japan
Prior art keywords
input
output
processor
memory
bus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP584279A
Other languages
Japanese (ja)
Inventor
Ichiro Yagami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP584279A priority Critical patent/JPS5597629A/en
Publication of JPS5597629A publication Critical patent/JPS5597629A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

PURPOSE: To shorten the execution time for the program which attains the desired control function by securing the independent and parallel operation for several processor units, thus obtaining the good response properties.
CONSTITUTION: Processor units 1.1, 1.2W1.n have operation independently based on the programs stored in proper memories 2.1, 2.2W2.n each, and also performs the data transfer to input/output data memory 5 via processor bus 3 and under the control of processor controller 4. Input/output controller 6 carries out the data transfer to memory 5 independently from processors 1.1, 1.2W1.n. Then the output signals sent from these processor units are delivered to input/output control bus 7, and at the same time the input signals are received from input/output modules 8.1, 8.2W8.n via bus 7 to be transferred to memory 5.
COPYRIGHT: (C)1980,JPO&Japio
JP584279A 1979-01-22 1979-01-22 Programmable control unit Pending JPS5597629A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP584279A JPS5597629A (en) 1979-01-22 1979-01-22 Programmable control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP584279A JPS5597629A (en) 1979-01-22 1979-01-22 Programmable control unit

Publications (1)

Publication Number Publication Date
JPS5597629A true JPS5597629A (en) 1980-07-25

Family

ID=11622263

Family Applications (1)

Application Number Title Priority Date Filing Date
JP584279A Pending JPS5597629A (en) 1979-01-22 1979-01-22 Programmable control unit

Country Status (1)

Country Link
JP (1) JPS5597629A (en)

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