JPS55946A - Adder with parity generating circuit part for binary-decimal addition result - Google Patents

Adder with parity generating circuit part for binary-decimal addition result

Info

Publication number
JPS55946A
JPS55946A JP7396878A JP7396878A JPS55946A JP S55946 A JPS55946 A JP S55946A JP 7396878 A JP7396878 A JP 7396878A JP 7396878 A JP7396878 A JP 7396878A JP S55946 A JPS55946 A JP S55946A
Authority
JP
Japan
Prior art keywords
bit
parity
item
binary
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7396878A
Other languages
Japanese (ja)
Other versions
JPS5613336B2 (en
Inventor
Shigemi Uemoto
Toshio Hayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7396878A priority Critical patent/JPS55946A/en
Publication of JPS55946A publication Critical patent/JPS55946A/en
Publication of JPS5613336B2 publication Critical patent/JPS5613336B2/ja
Granted legal-status Critical Current

Links

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  • Detection And Correction Of Errors (AREA)

Abstract

PURPOSE: To generate the parity bit of a binary-decimal addition result at a high speed by composing the circuit of a partial adder which sums up an addend and augend, bit by bit, a carry look ahead circuit, and a parity-bit and parity correction item generating circuit.
CONSTITUTION: Augends a0 to a15 and addends b0 to b15 are inputted, four bits by four bits, to partial adders 1 to 4 for one digit and group generating item CG and group proper gate item GP from adders 1 to 4 are inputted to carry look-ahead circuit 5. On the basis of augend bit ai and addend bit bi, bit generating item Gi and bit proper gate item are obtained and the both and parity bits Pa0, Pa1, Pb0, and Pb1 equivalent to 8-bit units of augends and addends are inputted to parity generating circuit 6 for binary addition results and parity correction item circuit 7 correcting a parity bit error at the time of decimal addition, thereby obtaining S0 to S15 of binary addition results of addition results, parity bits PS0 and PS1, and parity correction items P10 to P13.
COPYRIGHT: (C)1980,JPO&Japio
JP7396878A 1978-06-19 1978-06-19 Adder with parity generating circuit part for binary-decimal addition result Granted JPS55946A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7396878A JPS55946A (en) 1978-06-19 1978-06-19 Adder with parity generating circuit part for binary-decimal addition result

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7396878A JPS55946A (en) 1978-06-19 1978-06-19 Adder with parity generating circuit part for binary-decimal addition result

Publications (2)

Publication Number Publication Date
JPS55946A true JPS55946A (en) 1980-01-07
JPS5613336B2 JPS5613336B2 (en) 1981-03-27

Family

ID=13533377

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7396878A Granted JPS55946A (en) 1978-06-19 1978-06-19 Adder with parity generating circuit part for binary-decimal addition result

Country Status (1)

Country Link
JP (1) JPS55946A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH038019A (en) * 1989-06-06 1991-01-16 Nec Corp Adder circuit inspecting system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH038019A (en) * 1989-06-06 1991-01-16 Nec Corp Adder circuit inspecting system

Also Published As

Publication number Publication date
JPS5613336B2 (en) 1981-03-27

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